Patents by Inventor Shigenobu Maeda

Shigenobu Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150214340
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device includes forming a semiconductor layer on a fin, where the fin and the semiconductor layer include first and second semiconductor materials, respectively. Moreover, the method includes defining first and second active fins that include the second semiconductor material, by removing at least a portion of the fin. Related semiconductor devices are also provided.
    Type: Application
    Filed: January 20, 2015
    Publication date: July 30, 2015
    Inventors: Shigenobu Maeda, Bo-Ram Kim
  • Patent number: 9093306
    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: July 28, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Jeong Hwan Yang
  • Patent number: 9087842
    Abstract: A semiconductor device includes a substrate having a fuse area and a device area; a fuse structure in an insulating layer of the fuse area, and a wire structure in the insulating layer of the device area. The fuse structure includes a fuse via, a fuse line electrically connected to a top end of the fuse via pattern and extending in a direction. The wire structure includes a wire via, a wire line electrically connected to a top end of the wire via and extending in the first direction. A width in the first direction of the fuse via is smaller than a width in the first direction of the wire via.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: July 21, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Min Choi, Shigenobu Maeda, Ji-Hoon Yoon, Sung-Man Lim
  • Publication number: 20150144862
    Abstract: A variable resistance memory device includes a gate pattern and a dummy gate pattern provided at the same level on a substrate, a first contact pattern provided on the dummy gate pattern, and a variable resistance pattern provided between the dummy gate pattern and the first contact pattern. The gate pattern and the dummy gate pattern define conductive electrodes of functional and non-functional transistors, respectively. The first contact pattern and the dummy gate pattern define upper and lower electrodes on the variable resistance pattern, respectively. Related fabrication methods are also discussed.
    Type: Application
    Filed: October 29, 2014
    Publication date: May 28, 2015
    Inventors: Hyun-Min Choi, Juyoun Kim, Shigenobu Maeda, Jihoon Yoon, Sungman Lim
  • Publication number: 20150123209
    Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 7, 2015
    Inventors: Hyun-Min CHOI, Shigenobu MAEDA, Jihoon YOON, SUNGMAN LIM
  • Publication number: 20150123176
    Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.
    Type: Application
    Filed: January 14, 2015
    Publication date: May 7, 2015
    Inventors: Shigenobu Maeda, Hidenobu Fukutome, Young-Gun Ko, Joo-Hyun Jeong
  • Publication number: 20150118817
    Abstract: A method for fabricating a semiconductor device is provided, which includes forming a screen layer on a substrate, the screen layer including a first portion doped with a first type impurity, forming a first undoped semiconductor layer on the screen layer, forming a gate structure on the first semiconductor layer, forming a first amorphous region on both sides of the gate structure in the first semiconductor layer, and re-crystallizing the first amorphous region through performing a first heat treatment of the first amorphous region.
    Type: Application
    Filed: May 23, 2014
    Publication date: April 30, 2015
    Inventors: Kiyotaka IMAI, Young-Gwon KIM, Shigenobu MAEDA, Soon-Chul HWANG
  • Publication number: 20150108602
    Abstract: A semiconductor device includes a substrate having a fuse area and a device area; a fuse structure in an insulating layer of the fuse area, and a wire structure in the insulating layer of the device area. The fuse structure includes a fuse via, a fuse line electrically connected to a top end of the fuse via pattern and extending in a direction. The wire structure includes a wire via, a wire line electrically connected to a top end of the wire via and extending in the first direction. A width in the first direction of the fuse via is smaller than a width in the first direction of the wire via.
    Type: Application
    Filed: June 13, 2014
    Publication date: April 23, 2015
    Inventors: Hyun-Min CHOI, Shigenobu MAEDA, Ji-Hoon YOON, Sung-Man LIM
  • Publication number: 20150102458
    Abstract: Provided is an e-fuse structure of a semiconductor device. the e-fuse structure may include a fuse link formed of a first metal material to connect a cathode with an anode, a capping dielectric covering a top surface of the fuse link, and a dummy metal plug penetrating the capping dielectric and being in contact with a portion of the fuse link. The dummy metal plug may include a metal layer and a barrier metal layer interposed between the metal layer and the fuse link. The barrier metal layer may be formed of a second metal material different from the first metal material.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 16, 2015
    Inventors: Hyun-Min CHOI, Shigenobu MAEDA
  • Publication number: 20150076655
    Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.
    Type: Application
    Filed: April 25, 2014
    Publication date: March 19, 2015
    Inventors: Hyun-Min Choi, Shigenobu MAEDA
  • Patent number: 8962435
    Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Hidenobu Fukutome, Young-Gun Ko, Joo-Hyun Jeong
  • Publication number: 20150024565
    Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.
    Type: Application
    Filed: October 7, 2014
    Publication date: January 22, 2015
    Inventors: Shigenobu Maeda, Hidenobu Fukutome, Young-Gun Ko, Joo-Hyun Jeong
  • Publication number: 20150014788
    Abstract: A semiconductor device includes a gate on a substrate, a gate insulating layer along a sidewall and a bottom surface of the gate, and an L-shaped spacer structure on both sidewalls of the gate. A structure extends the distance between the gate and source/drain regions to either side of the gate.
    Type: Application
    Filed: January 29, 2014
    Publication date: January 15, 2015
    Inventors: Min-Yeop Park, Leonelli Daniele, Shigenobu Maeda, Han-Su Oh, Woong-Gi Kim, Jong-Hyuk Lee, Ju-Seob Jeong
  • Publication number: 20140357035
    Abstract: Provided are a semiconductor device including a high voltage transistor and a low voltage transistor and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate including a high voltage region and a low voltage region; a high voltage transistor formed in the high voltage region and including a first active region, a first source/drain region, a first gate insulating layer, and a first gate electrode; and a low voltage transistor formed in the low voltage region and including a second active region, a second source/drain region, a second gate insulating layer, and a second gate electrode. The second source/drain region has a smaller thickness than a thickness of the first source/drain region.
    Type: Application
    Filed: August 14, 2014
    Publication date: December 4, 2014
    Inventors: Shigenobu MAEDA, Hyun-pil NOH, Choong-ho LEE, Seog-heon HAM
  • Publication number: 20140353769
    Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.
    Type: Application
    Filed: August 19, 2014
    Publication date: December 4, 2014
    Inventors: Shigenobu Maeda, Hee-Soo Kang, Sang-Pil Sim, Soo-Hun Hong
  • Publication number: 20140346602
    Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.
    Type: Application
    Filed: August 13, 2014
    Publication date: November 27, 2014
    Inventors: Shigenobu Maeda, Hee-Soo Kang, Sang-Pil Sim, Soo-Hun Hong
  • Publication number: 20140332897
    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.
    Type: Application
    Filed: July 22, 2014
    Publication date: November 13, 2014
    Inventors: Shigenobu Maeda, Jeong Hwan Yang
  • Patent number: 8884298
    Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Hidenobu Fukutome, Young-Gun Ko, Joo-Hyun Jeong
  • Publication number: 20140312427
    Abstract: Semiconductor devices are provided. The semiconductor devices include a first fin; a first gate electrode intersecting the first fin; a first elevated source and/or drain on respective sides of the first gate electrode on the first fin; and a first field dielectric film adjacent the first fin. The first field dielectric film includes a first part below a top surface of the first fin and a second part protruding from the first part and above a top surface of the first fin that makes contact with the first elevated source and/or drain.
    Type: Application
    Filed: April 23, 2014
    Publication date: October 23, 2014
    Inventors: Shigenobu Maeda, Sung-Bong Kim, Chang-Wook Moon, Dong-Hun Lee, Hyung-Soon Jang, Sang-Pil Sim
  • Patent number: 8836046
    Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Hee-Soo Kang, Sang-Pil Sim, Soo-Hun Hong