Patents by Inventor Shigenori Hayakawa
Shigenori Hayakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230006425Abstract: A semiconductor optical device includes a substrate of a first conductivity type; an optical confinement layer of the first conductivity type, which is arranged above the substrate of the first conductivity type; a multi quantum well layer, which is arranged above the optical confinement layer of the first conductivity type, and comprises a plurality of well layers and a plurality of barrier layers; an optical confinement layer of a second conductivity type, which is arranged on the multi quantum well layer; and a PL stabilization layer, which is arranged between the substrate of the first conductivity type and the multi quantum well layer. The PL stabilization layer having a thickness that is half a thickness of the multi quantum well layer or more, and having a composition wavelength that is shorter than a composition wavelength of the plurality of well layers of the multi quantum well layer.Type: ApplicationFiled: January 21, 2022Publication date: January 5, 2023Inventors: Hironori SAKAMOTO, Shigenori HAYAKAWA
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Patent number: 11462886Abstract: A buried semiconductor optical device comprises a semiconductor substrate; a mesa-stripe portion including a multi-quantum well layer on the semiconductor substrate; a buried layer consisting of a first portion and a second portion, the first portion covering one side of the mesa-stripe portion, the second portion covering the other side of the mesa-stripe portion, and the first portion and the second portion covering a surface of the semiconductor substrate; and an electrode configured to cause an electric current to flow through the mesa-stripe portion, the buried layer comprising, from the surface, a first, second, and third sublayer, the first and third sublayer each consisting of semi-insulating InP, the first sublayer and the second sublayer forming a pair structure, the second sublayer being located above the multi-quantum well layer, and the second sublayer consisting of one or more layers selected from InGaAs, InAlAs, InGaAlAs, InGaAsP, and InAlAsP.Type: GrantFiled: April 10, 2020Date of Patent: October 4, 2022Assignee: Lumentum Japan, Inc.Inventors: Shigenori Hayakawa, Hironori Sakamoto, Shunya Yamauchi, Yoshihiro Nakai
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Patent number: 11329450Abstract: A electro-absorption optical modulator includes a multiple quantum well composed of a plurality of layers including a plurality of quantum well layers and a plurality of barrier layers that are alternately stacked, the plurality of quantum well layers and the plurality of barrier layers including an acceptor and a donor; a p-type semiconductor layer in contact with an uppermost layer of the plurality of layers; and an n-type semiconductor layer in contact with a lowermost layer of the plurality of layers, the multiple quantum well being 10% or more and 150% or less of the p-type semiconductor layer in a p-type carrier concentration, and in the multiple quantum well, an effective carrier concentration which corresponds to a difference between the p-type carrier concentration and an n-type carrier concentration is ±10% or less of the p-type carrier concentration of the multiple quantum well.Type: GrantFiled: April 10, 2020Date of Patent: May 10, 2022Assignee: Lumentum Japan, Inc.Inventors: Atsushi Nakamura, Takeshi Kitatani, Kaoru Okamoto, Shigenori Hayakawa
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Publication number: 20220006257Abstract: The upper surface of the semiconductor substrate has a slope descending from the projection in the second direction at an angle of 0-12° to a horizontal plane. The mesa stripe structure has an inclined surface with a slope ascending from the upper surface of the semiconductor substrate at an angle of 45-55° to the horizontal plane, the mesa stripe structure having an upright surface rising from the inclined surface at an angle of 85-95° to the horizontal plane. The buried layer is made from semiconductor with ruthenium doped therein and is in contact with the inclined surface and the upright surface. The inclined surface is as high as 80% or less of height from the upper surface of the semiconductor substrate to a lower surface of the quantum well layer and is as high as 0.3 ?m or more.Type: ApplicationFiled: September 17, 2021Publication date: January 6, 2022Inventors: Takafumi TANIGUCHI, Shigenori HAYAKAWA, Yasushi SAKUMA
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Patent number: 11133646Abstract: The upper surface of the semiconductor substrate has a slope descending from the projection in the second direction at an angle of 0-12° to a horizontal plane. The mesa stripe structure has an inclined surface with a slope ascending from the upper surface of the semiconductor substrate at an angle of 45-55° to the horizontal plane, the mesa stripe structure having an upright surface rising from the inclined surface at an angle of 85-95° to the horizontal plane. The buried layer is made from semiconductor with ruthenium doped therein and is in contact with the inclined surface and the upright surface. The inclined surface is as high as 80% or less of height from the upper surface of the semiconductor substrate to a lower surface of the quantum well layer and is as high as 0.3 ?m or more.Type: GrantFiled: May 22, 2019Date of Patent: September 28, 2021Assignee: Lumentum Japan, Inc.Inventors: Takafumi Taniguchi, Shigenori Hayakawa, Yasushi Sakuma
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Publication number: 20210057885Abstract: A electro-absorption optical modulator includes a multiple quantum well composed of a plurality of layers including a plurality of quantum well layers and a plurality of barrier layers that are alternately stacked, the plurality of quantum well layers and the plurality of barrier layers including an acceptor and a donor; a p-type semiconductor layer in contact with an uppermost layer of the plurality of layers; and an n-type semiconductor layer in contact with a lowermost layer of the plurality of layers, the multiple quantum well being 10% or more and 150% or less of the p-type semiconductor layer in a p-type carrier concentration, and in the multiple quantum well, an effective carrier concentration which corresponds to a difference between the p-type carrier concentration and an n-type carrier concentration is ±10% or less of the p-type carrier concentration of the multiple quantum well.Type: ApplicationFiled: April 10, 2020Publication date: February 25, 2021Inventors: Atsushi NAKAMURA, Takeshi KITATANI, Kaoru OKAMOTO, Shigenori HAYAKAWA
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Publication number: 20210044083Abstract: A buried semiconductor optical device comprises a semiconductor substrate; a mesa-stripe portion including a multi-quantum well layer on the semiconductor substrate; a buried layer consisting of a first portion and a second portion, the first portion covering one side of the mesa-stripe portion, the second portion covering the other side of the mesa-stripe portion, and the first portion and the second portion covering a surface of the semiconductor substrate; and an electrode configured to cause an electric current to flow through the mesa-stripe portion, the buried layer comprising, from the surface of the semiconductor substrate, a first sublayer, a second sublayer, and a third sublayer, the first sublayer, the second sublayer, and the third sublayer each consisting of semi-insulating InP, the first sublayer and the second sublayer forming a pair structure, the second sublayer being located above the multi-quantum well layer from the surface of the semiconductor substrate, and the second sublayer consistingType: ApplicationFiled: April 10, 2020Publication date: February 11, 2021Inventors: Shigenori HAYAKAWA, Hironori SAKAMOTO, Shunya YAMAUCHI, Yoshihiro NAKAI
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Publication number: 20200044417Abstract: The upper surface of the semiconductor substrate has a slope descending from the projection in the second direction at an angle of 0-12° to a horizontal plane. The mesa stripe structure has an inclined surface with a slope ascending from the upper surface of the semiconductor substrate at an angle of 45-55° to the horizontal plane, the mesa stripe structure having an upright surface rising from the inclined surface at an angle of 85-95° to the horizontal plane. The buried layer is made from semiconductor with ruthenium doped therein and is in contact with the inclined surface and the upright surface. The inclined surface is as high as 80% or less of height from the upper surface of the semiconductor substrate to a lower surface of the quantum well layer and is as high as 0.3 ?m or more.Type: ApplicationFiled: May 22, 2019Publication date: February 6, 2020Inventors: Takafumi TANIGUCHI, Shigenori HAYAKAWA, Yasushi SAKUMA
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Patent number: 10230008Abstract: Provided are a semiconductor light receiving device, an optical receiver module, and a manufacturing method thereof in which characteristics of the device are improved when the device has a structure in which a mesa structure including layers formed of a common material is buried by a buried layer. The semiconductor light receiving device includes the mesa structure including the layers formed of a commonmaterial, the layers including an absorbing layer, the mesa structure being buried by the buried layer formed so as to surround side surfaces of the mesa structure. The mesa structure has a cross section having a forwardly tapered portion and a reversely tapered portion.Type: GrantFiled: February 12, 2016Date of Patent: March 12, 2019Assignee: Oclaro Japan, Inc.Inventors: Masahiro Ebisu, Hiroshi Hamada, Yasushi Sakuma, Shigenori Hayakawa
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Publication number: 20160240698Abstract: Provided are a semiconductor light receiving device, an optical receiver module, and a manufacturing method thereof in which characteristics of the device are improved when the device has a structure in which a mesa structure including layers formed of a common material is buried by a buried layer. The semiconductor light receiving device includes the mesa structure including the layers formed of a commonmaterial, the layers including an absorbing layer, the mesa structure being buried by the buried layer formed so as to surround side surfaces of the mesa structure. The mesa structure has a cross section having a forwardly tapered portion and a reversely tapered portion.Type: ApplicationFiled: February 12, 2016Publication date: August 18, 2016Inventors: Masahiro EBISU, Hiroshi HAMADA, Yasushi SAKUMA, Shigenori HAYAKAWA
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Patent number: 8488918Abstract: Provided is a semiconductor optical device, which has a buried heterostructure structure and is formed in a structure capable of reducing a parasitic capacitance to further improve characteristics thereof, and also provided are an optical transmitter module, an optical transceiver module, and an optical transmission equipment. The semiconductor optical device includes a modulator portion for modulating light input along an emitting direction and radiating the modulated light, the modulator portion including: a mesa-stripe structure, which includes an active layer and extends in the emitting direction; and a buried layer provided adjacent to each side of the mesa-stripe structure, in which a distance between a lower surface of the buried layer and a lower surface of the active layer is 20% or more of a distance between the lower surface and an upper surface of the buried layer.Type: GrantFiled: May 16, 2011Date of Patent: July 16, 2013Assignee: Oclaro Japan, Inc.Inventors: Seiji Sumi, Shigenori Hayakawa, Kaoru Okamoto, Shunya Yamauchi, Yasushi Sakuma
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Publication number: 20120008895Abstract: Provided is a semiconductor optical device, which has a buried heterostructure structure and is formed in a structure capable of reducing a parasitic capacitance to further improve characteristics thereof, and also provided are an optical transmitter module, an optical transceiver module, and an optical transmission equipment. The semiconductor optical device includes a modulator portion for modulating light input along an emitting direction and radiating the modulated light, the modulator portion including: a mesa-stripe structure, which includes an active layer and extends in the emitting direction; and a buried layer provided adjacent to each side of the mesa-stripe structure, in which a distance between a lower surface of the buried layer and a lower surface of the active layer is 20% or more of a distance between the lower surface and an upper surface of the buried layer.Type: ApplicationFiled: May 16, 2011Publication date: January 12, 2012Applicant: OPNEXT JAPAN, INC.Inventors: Seiji SUMI, Shigenori HAYAKAWA, Kaoru OKAMOTO, Shunya YAMAUCHI, Yasushi SAKUMA
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Patent number: 7998766Abstract: A semiconductor element and a manufacturing method of the semiconductor element are provided. A ridge waveguide type semiconductor integrated element includes: an electrode of an EA portion and an electrode of an LD portion which are arranged so as to be away from each other; a contact layer of the EA portion and a contact layer of the LD portion which are arranged so as to be away from each other and in each of which the electrode is formed on an upper surface and an edge of at least a part of the upper surface is set to the same electric potential as that of the electrode; a passivation film as an insulative concave/convex structure extending from an edge of one of the two contact layers to an edge of the other contact layer; and a polyimide resin for embedding the passivation film.Type: GrantFiled: April 24, 2008Date of Patent: August 16, 2011Assignee: OpNext Japan, Inc.Inventors: Yasushi Sakuma, Daisuke Nakai, Shigenori Hayakawa, Kazuhiro Komatsu
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Patent number: 7772052Abstract: There is provided a method of manufacturing a semiconductor device, in which removal of the resist after ion implantation becomes easy. In order to solve the above problem, the manufacturing method includes a step of removing a resist mask after a step of implanting an ion of a rare gas element. Also, another manufacturing method includes a first step of implanting an ion of an impurity element for imparting a conductivity type, a second step of implanting an ion of a rare gas element, and a third step of removing a resist mask after the first step and the second step.Type: GrantFiled: November 9, 2004Date of Patent: August 10, 2010Assignee: Semiconductor Energy Laboratory Co., LtdInventor: Shigenori Hayakawa
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Patent number: 7687295Abstract: In an optical semiconductor device that emits or receives light substantially perpendicularly to or in parallel to an active surface formed on a semiconductor substrate, the optical semiconductor device, an electrode that is formed on the active surface side and connected to the active surface is stepped or tapered at an end of the electrode. The electrode of the optical semiconductor device is formed of three layers including an adhesive layer, a diffusion prevention layer, and an Au layer, and the stepped configuration or the taped configuration is formed by a difference of the thickness of the Au layer or the thickness of the adhesive layer/diffusion prevention layer/Au layer.Type: GrantFiled: January 31, 2008Date of Patent: March 30, 2010Assignee: Opnext Japan, Inc.Inventors: Ryu Washino, Susumu Sorimachi, Daisuke Nakai, Kaoru Okamoto, Shigenori Hayakawa
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Patent number: 7615473Abstract: When an ion is introduced into a semiconductor on which a resist is formed, the ion and the resist react with each other to generate a gas (dissociated gas) and a component of the thus-generated dissociated gas is introduced into the semiconductor, which becomes a factor to deteriorate properties of the semiconductor. According to the invention, the dissociated gas to be generated from an organic film is treated. Particularly, the dissociated gas is treated before an ion introduction is performed. As a method of performing such a treatment, the ion introduction is performed by dividing ion introduction processing itself into a plurality of times. The dissociated gas is generated in a maximum quantity just after the ion introduction is started.Type: GrantFiled: January 16, 2003Date of Patent: November 10, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shigenori Hayakawa
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Publication number: 20090065901Abstract: A semiconductor element and a manufacturing method of the semiconductor element are provided. A ridge waveguide type semiconductor integrated element includes: an electrode of an EA portion and an electrode of an LD portion which are arranged so as to be away from each other; a contact layer of the EA portion and a contact layer of the LD portion which are arranged so as to be away from each other and in each of which the electrode is formed on an upper surface and an edge of at least a part of the upper surface is set to the same electric potential as that of the electrode; a passivation film as an insulative concave/convex structure extending from an edge of one of the two contact layers to an edge of the other contact layer; and a polyimide resin for embedding the passivation film.Type: ApplicationFiled: April 24, 2008Publication date: March 12, 2009Inventors: Yasushi Sakuma, Daisuke Nakai, Shigenori Hayakawa, Kazuhiro Komatsu
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Publication number: 20080203404Abstract: In an optical semiconductor device that emits or receives light substantially perpendicularly to or in parallel to an active surface formed on a semiconductor substrate, the optical semiconductor device, an electrode that is formed on the active surface side and connected to the active surface is stepped or tapered at an end of the electrode. The electrode of the optical semiconductor device is formed of three layers including an adhesive layer, a diffusion prevention layer, and an Au layer, and the stepped configuration or the taped configuration is formed by a difference of the thickness of the Au layer or the thickness of the adhesive layer/diffusion prevention layer/Au layer.Type: ApplicationFiled: January 31, 2008Publication date: August 28, 2008Inventors: Ryu Washino, Susumu Sorimachi, Daisuke Nakai, Kaoru Okamoto, Shigenori Hayakawa
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Publication number: 20080036044Abstract: To eliminate generation of a damaged layer caused by dry etching of a contact layer, occurring in a manufacturing process of a ridge waveguide type semiconductor laser, and to improve reliability and yield thereof, a method is provided involving forming a spacer layer and a damage receptor layer on the contact layer, making the two layer absorb damage caused by dry etching a passivation film in an upper portion of the ridge waveguide structure, and thereafter removing the damaged layer by the dry etching, by selective removal by wet etching.Type: ApplicationFiled: August 1, 2007Publication date: February 14, 2008Inventors: Yasushi Sakuma, Kazuhiro Komatsu, Shigenori Hayakawa, Daisuke Nakai
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Publication number: 20050064685Abstract: There is provided a method of manufacturing a semiconductor device, in which removal of the resist after ion implantation becomes easy. In order to solve the above problem, the manufacturing method includes a step of removing a resist mask after a step of implanting an ion of a rare gas element. Also, another manufacturing method includes a first step of implanting an ion of an impurity element for imparting a conductivity type, a second step of implanting an ion of a rare gas element, and a third step of removing a resist mask after the first step and the second step.Type: ApplicationFiled: November 9, 2004Publication date: March 24, 2005Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shigenori Hayakawa