Abstract: 512 clusters included in one segment are distributed into 128 clusters included in each of four storages. A logical/physical address conversion table is formed every segment. Therefore, unless the segment is changed, the logical/physical address conversion table to be referred to or updated does not change, so that a deterioration of the reading performance due to an access to the table or an updating of the table can be prevented. Data can be simultaneously written into continuous logic cluster addresses, for example, 0x0004 to 0x0007, and the high speed writing operation can be realized.

Abstract: This invention provides a memory card (1) that is to be used as a storage medium in a host apparatus that can record and reproduce data. The memory card has a first memory (12-1), a second memory (12-2), a first switch (13) for changing over one memory to the other, and a second switch (14) for connecting and disconnecting an insertion/removal detecting terminal INS. The first and second switches work as a slide switch (6) provided on the housing is operated. The first switch has a contact for selecting the first memory, a contact for selecting the second memory, and a contact located between these two contacts, for selecting neither memory. The second switch connects the terminal INS to the ground while the first switch remains connected to the contact for selecting the first memory or the contact for selecting the second memory. The second switch opens the terminal INS while the first switch remains connected to the contact for selecting neither memory.

Abstract: Data 30 is recorded into storages 0 to 3 in parallel. Writing sectors are selected from a plurality of clusters so that the sectors are continuously arranged in each cluster, and the data is simultaneously written into the selected sectors. In the case where the sectors numbered in the original order are written into the storages 0 to 3 in parallel, the data of No. 0 is recorded into the head sector in the cluster of the storage 0, the data of No. 16 is recorded into the head sector in the cluster of the storage 1, the data of No. 32 is recorded into the head sector in the cluster of the storage 2, and the data of No. 48 is recorded into the head sector in the cluster of the storage 3, respectively. Thus, the data is arranged in the original order into the cluster constructed in the same storage. When the data is written into a plurality of storages in parallel, the compatibility of the file format of the written data is held.

Abstract: Data 30 is recorded into storages 0 to 3 in parallel. Writing sectors are selected from a plurality of clusters so that the sectors are continuously arranged in each cluster, and the data is simultaneously written into the selected sectors. In the case where the sectors numbered in the original order are written into the storages 0 to 3 in parallel, the data of No. 0 is recorded into the head sector in the cluster of the storage 0, the data of No. 16 is recorded into the head sector in the cluster of the storage 1, the data of No. 32 is recorded into the head sector in the cluster of the storage 2, and the data of No. 48 is recorded into the head sector in the cluster of the storage 3, respectively. Thus, the data is arranged in the original order into the cluster constructed in the same storage. When the data is written into a plurality of storages in parallel, the compatibility of the file format of the written data is held.

Abstract: Data 30 is recorded into storages 0 to 3 in parallel. Writing sectors are selected from a plurality of clusters so that the sectors are continuously arranged in each cluster, and the data is simultaneously written into the selected sectors. In the case where the sectors numbered in the original order are written into the storages 0 to 3 in parallel, the data of No. 0 is recorded into the head sector in the cluster of the storage 0, the data of No. 16 is recorded into the head sector in the cluster of the storage 1, the data of No. 32 is recorded into the head sector in the cluster of the storage 2, and the data of No. 48 is recorded into the head sector in the cluster of the storage 3, respectively. Thus, the data is arranged in the original order into the cluster constructed in the same storage. When the data is written into a plurality of storages in parallel, the compatibility of the file format of the written data is held.

Abstract: A semiconductor memory device of the present invention includes bit lines and common data lines for data writing or readout into or from plural memory cells. On these bit lines and common data lines, equalizing or precharging circuits are provided and operate during address transition. During transition from writing to readout, such transition is detected to actuate the equalizing or precharging circuits more promptly than usual to shorten the write recovery time to realize a high speed operation. The output circuit of the semiconductor memory device of the present invention is provided with a precharging circuit for sensing and precharging the level on the output terminal to an intermediate level. The output circuit of this construction allows to reduce the power consumption and to assure a high speed outputting operation.

Abstract: The invention provides a static random access memory wherein the peak value of current flow therethrough upon flash-clearing is minimized. The static random access memory comprises a memory cell array which is divided into a plurality of memory cell groups which are driven at mutually different timings for flash-clearing by means of a plurality of delay circuits connected in cascade to which the flash-clearing signal is applied.

Abstract: In a bit line driver for MOS memory units of a microcomputer, which is connected between a pair of complementary bit lines and provided with an equalizing MOS transistor, a pair of active-load MOS transistors and a pair of clamping MOS transistors are connected separately to the complementary bit lines, and further the area of the clamping MOS transistors is determined to be about three times greater than that of the active-load transistors. An increase in the area of the clamping MOS transistors serves to decrease the internal resistance thereof, so that the clamping operation can be improved. A decrease in area of the active-load MOS transistor serves to increase the internal resistance, so that the access time can be improved. In addition, the driver can operate stably in response to a low power clock pulse.

Abstract: An electrode type steam vaporizer device is disclosed which includes a plurality of ferrite electrodes positioned in a water receptacle wherein AC voltage is applied to the electrodes thereby vaporizing water in the receptacle. Each of the ferrite electrodes is a sintered body made of a mixture of iron oxide and a divalent nickel oxide. The ferrite electrodes are contained in an electrode assembly located within the body of the water receptacle such that a pair of electrode terminals extend through the top wall of the receptacle. A cover having a power source connector receiving concavity in its surface is positioned on top on the water receptacle. The cover is rotatable between a first position where the concavity is in registry with the electrode terminals and a second position where the concavity is out of registry with the terminals. A power source connector is received in the concavity and is connectable with the electrode terminals only when the cover is in the first position.