Abstract: Each of a plurality of circuit blocks includes a plurality of arithmetic elements. A power supply controller individually controls power supply to each circuit block. A resource management unit acquires first information, regarding an arithmetic element necessary for an arithmetic process, and second information, regarding an arithmetic element included in a circuit block which is currently being supplied with power. Based on the first information and the second information, the resource management unit preferentially assigns, to an arithmetic element included in a circuit block which is being supplied with power, a process for implementing the arithmetic process.

Abstract: An information processing apparatus for determining polarity of a vertical synchronizing signal, in an effective state, included in a video signal measures a duration in which the vertical synchronizing signal maintains the same polarity, obtains the polarity of the vertical synchronizing signal when the measured duration exceeds a predetermined duration, and determines the polarity of the vertical synchronizing signal in the effective state based on the obtained polarity.

Abstract: An information processing apparatus for determining polarity of a vertical synchronizing signal, in an effective state, included in a video signal measures a duration in which the vertical synchronizing signal maintains the same polarity, obtains the polarity of the vertical synchronizing signal when the measured duration exceeds a predetermined duration, and determines the polarity of the vertical synchronizing signal in the effective state based on the obtained polarity.

Abstract: This invention includes a clock tree to which clock signals are distributed, and a phase comparison circuit configured to detect the phase difference between a plurality of feedback clock signals upon receiving the plurality of feedback clock signals output from different branching points of the clock tree. The invention includes a feedback clock signal generation circuit configured to generate a variation-corrected feedback clock signal for correcting a manufacture variation in the semiconductor integrated circuit based on the phase difference detected by the phase comparison circuit. The invention includes a phase regulation circuit configured to delay the clock signal so as to reduce the phase difference between a reference clock signal and the variation-corrected feedback clock signal generated by the feedback clock signal generation circuit.

Abstract: Each of a plurality of circuit blocks includes a plurality of arithmetic elements. A power supply controller individually controls power supply to the plurality of circuit blocks. A resource management unit acquires first information regarding an arithmetic element necessary for an arithmetic process, and second information regarding an arithmetic element included in a circuit block which is supplied with power. Based on the first information and the second information, the resource management unit preferentially assigns, to the arithmetic element included in the circuit block which is supplied with power, a process for implementing the arithmetic process.

Abstract: This invention includes a clock tree to which clock signals are distributed, and a phase comparison circuit configured to detect the phase difference between a plurality of feedback clock signals upon receiving the plurality of feedback clock signals output from different branching points of the clock tree. The invention includes a feedback clock signal generation circuit configured to generate a variation-corrected feedback clock signal for correcting a manufacture variation in the semiconductor integrated circuit based on the phase difference detected by the phase comparison circuit. The invention includes a phase regulation circuit configured to delay the clock signal so as to reduce the phase difference between a reference clock signal and the variation-corrected feedback clock signal generated by the feedback clock signal generation circuit.