Patents by Inventor Shigeo Kondo

Shigeo Kondo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10431590
    Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: October 1, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
  • Patent number: 10395739
    Abstract: According to an embodiment, a semiconductor memory device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a word line driving circuit, a sense amplifier circuit, and a controller. The memory cell connected to the selected word line is written with data using a write sequence including a plurality of write loops each including a write operation of applying a write voltage to the selected word line by the word line driving circuit and a verify operation of detecting data of the memory cell by the sense amplifier circuit. The controller determines an (n+k)-th (where n is an integer not less than 1 and k is an integer not less than 2) verify operation based on comparison between an n-th verify operation and an (n+1)-th verify operation in the write sequence.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 27, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Shigeo Kondo
  • Patent number: 10360974
    Abstract: According to one embodiment, a semiconductor memory of an embodiment includes memory cells, a word line, bit lines, and a controller. The word line is coupled to a plurality of memory cells. The plurality of bit lines are respectively coupled to the plurality of memory cells. The controller executes a first write, and classifies a plurality of memory cells to which the second data should be written into a plurality of subgroups in accordance with a result of the first write, and after the classification, the controller executes a second write that includes a first program loop.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: July 23, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Shigeo Kondo
  • Publication number: 20190214405
    Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.
    Type: Application
    Filed: March 13, 2019
    Publication date: July 11, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kaito SHIRAI, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
  • Publication number: 20190160584
    Abstract: A center pipe is used in a plasma torch including a base portion and an electrode to supply cooling water into the electrode. The center pipe includes a pipe body and a contact piece. The pipe body has a tube-like shape with a cooling water channel therein. The pipe body is electrically conductive and configured to be electrically connected to an external power source via the base portion. The contact piece is arranged radially outside the pipe body at an intermediate position between a base end surface and a tip end surface of the pipe body. The contact piece is electrically conductive and energizes the electrode through contact with an internal circumferential surface of the electrode. The base end surface is disposed outside the electrode when the center pipe is inserted into the electrode. The pipe body is configured to be electrically connected to the electrode via the contact piece.
    Type: Application
    Filed: February 1, 2019
    Publication date: May 30, 2019
    Inventors: Yoshihiro YAMAGUCHI, Keita KONDO, Shigeo MORIMOTO, Katsuo SAIO
  • Publication number: 20190088313
    Abstract: According to one embodiment, a semiconductor memory of an embodiment includes memory cells, a word line, bit lines, and a controller. The word line is coupled to a plurality of memory cells. The plurality of bit lines are respectively coupled to the plurality of memory cells. The controller executes a first write, and classifies a plurality of memory cells to which the second data should be written into a plurality of subgroups in accordance with a result of the first write, and after the classification, the controller executes a second write that includes a first program loop.
    Type: Application
    Filed: March 8, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Shigeo KONDO
  • Publication number: 20180277222
    Abstract: According to an embodiment, a semiconductor memory device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a word line driving circuit, a sense amplifier circuit, and a controller. The memory cell connected to the selected word line is written with data using a write sequence including a plurality of write loops each including a write operation of applying a write voltage to the selected word line by the word line driving circuit and a verify operation of detecting data of the memory cell by the sense amplifier circuit. The controller determines an (n+k)-th (where n is an integer not less than 1 and k is an integer not less than 2) verify operation based on comparison between an n-th verify operation and an (n+1)-th verify operation in the write sequence.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 27, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Shigeo KONDO
  • Publication number: 20180277231
    Abstract: A word-line controller applies a voltage to a selected word-line. A bit-line controller applies voltages to bit-lines. A detector detects data of memory-cells. A write sequence of writing data in selected memory-cells connected to the selected word-line has at least one write-loop including a write operation of applying a plurality of write voltages with the word-line controller and the bit-line controller, and a verify operation of verifying with the detection circuit whether a threshold voltage of each of the selected memory-cells has reached a plurality of reference voltages for corresponding write data. The word-line controller and the bit-line controller select a write voltage corresponding to a threshold voltage of each of the selected memory-cells from among the write voltages with respect to each of the write-loops, and apply the selected write voltage to the selected memory-cell in a subsequent write operation.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 27, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Shigeo KONDO
  • Patent number: 9985044
    Abstract: A semiconductor memory device according to an embodiment, includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: May 29, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
  • Publication number: 20180130810
    Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
    Type: Application
    Filed: January 5, 2018
    Publication date: May 10, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
  • Patent number: 9966604
    Abstract: An electrochemical device manufactured using an electrode layer in which severe increase of electrode resistance is prevented and/or a solid electrolyte layer in which severe decrease of ion conductivity of a solid electrolyte is prevented is provided. The electrochemical device includes a pair of electrode layers, and a solid electrolyte layer provided between the pair of electrode layers, wherein at least one layer of the electrode layers and the solid electrolyte layer is composed of first particles each providing a function of the at least one layer, second particles and a binder which is composed of an organic polymer and binds the first and second particles, and wherein the at least one layer is formed from a mixture material containing the first particles and binder particles, each of the binder particles including the second particle and the binder carried on at least a part of a surface thereof.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: May 8, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Shigeo Kondo, Yasumasa Takeuchi, Yuji Shinohara, Takeo Kawase
  • Publication number: 20170263326
    Abstract: A memory device capable of narrowing the threshold voltage distribution thereof includes word lines, bit lines, memory cells, a word line driver configured to apply voltage to a selected word line, a sense amplifier circuit configured to detect data of the memory cell, and a controller configured to control the word line driver and the sense amplifier. A write sequence includes a write operation in which write voltage is applied to the selected word line by the word line driver, and a verify operation in which, when a threshold voltage of the selected memory cell reaches a reference voltage, writing to the selected memory cell is completed. Based on second data that is written later than the first data to an adjacent memory cell adjacent to the selected memory cell, the controller changes the reference voltage used for completing the writing to the selected memory cell.
    Type: Application
    Filed: August 31, 2016
    Publication date: September 14, 2017
    Inventor: Shigeo KONDO
  • Publication number: 20170263614
    Abstract: A semiconductor memory device according to an embodiment, includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
    Type: Application
    Filed: September 14, 2016
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: HIROKI TOKUHIRA, TAKAHISA KANEMURA, SHIGEO KONDO, MICHIRU HOGYOKU
  • Patent number: 9761318
    Abstract: A memory device capable of narrowing the threshold voltage distribution thereof includes word lines, bit lines, memory cells, a word line driver configured to apply voltage to a selected word line, a sense amplifier circuit configured to detect data of the memory cell, and a controller configured to control the word line driver and the sense amplifier. A write sequence includes a write operation in which write voltage is applied to the selected word line by the word line driver, and a verify operation in which, when a threshold voltage of the selected memory cell reaches a reference voltage, writing to the selected memory cell is completed. Based on second data that is written later than the first data to an adjacent memory cell adjacent to the selected memory cell, the controller changes the reference voltage used for completing the writing to the selected memory cell.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: September 12, 2017
    Assignee: Toshiba Memory Corporation
    Inventor: Shigeo Kondo
  • Patent number: 9640274
    Abstract: A semiconductor memory device includes word lines, bit lines, and memory cells at intersections of the word lines and the bit lines. A driver is configured to a voltage to a selected word line. A sense amplifier is configured to detect data of the memory cells. A controller is configured to control the driver and the sense amplifier. A writing sequence of writing data to a selected memory cell connected to the selected word line includes a plurality of writing loops including a write operation and a verify operation. The controller is configured to perform the write operation on the selected memory cell a predetermined number of times corresponding to write data to be written to the selected memory cell, without the verify operation, after a threshold voltage of the selected memory cell connected to the selected word line reaches a first level.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: May 2, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Shigeo Kondo
  • Patent number: 9257718
    Abstract: A secondary battery that can avoid reduction in battery capacity over the lapse of charge-discharge cycles and can exhibit high performance is provided. The secondary battery includes a laminated body having a pair of electrodes and an electrolyte layer provided between the pair of electrodes, the electrolyte layer including electrolyte particles, the laminated body having an end portion, and a restrictor provided so as to cover at least the end portion of the laminated body for restricting expansion of the electrolyte layer in the plane direction thereof.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: February 9, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Shigeo Kondo, Yasumasa Takeuchi
  • Publication number: 20160027512
    Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a control unit, during the read sequence performed to an interested cell, performing a first read operation to detect that a threshold voltage of an adjacent cell is higher than a second reference voltage higher, performing a second read operation to detect that the threshold voltage of the interested cell is higher than a first reference voltage while applying a first bit line voltage to the adjacent bit line when threshold voltages of the adjacent cells are lower than the second reference voltage, and to detect that the threshold voltage of the interested cell is higher than the first reference voltage while applying a second bit line voltage higher than the first bit line voltage to the adjacent bit line when threshold voltages of the adjacent cells are higher than the second reference voltage, after the first read operation.
    Type: Application
    Filed: October 27, 2014
    Publication date: January 28, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke HAGISHIMA, Mitsutoshi Nakamura, Shigeo Kondo, Michiru Hogyoku
  • Patent number: 9208887
    Abstract: A non-volatile semiconductor memory device according to one embodiment includes: a cell array; and a data writing unit that repeatedly executes a write loop including a programming operation of applying a program voltage to a selected word line and a passage voltage to non-selected word lines during writing of data, in which, when a difference between the passage voltage used in an n-th write loop and the passage voltage used in an n+1-th write loop is expressed as ?Vn and when a condition of L<M (L and M are integers) is satisfied, the data writing unit executes the write loop using the passage voltage where ?V (L?1)<?VL, ?VL??V (M?1), and ?V (M?1)<?VM.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: December 8, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Shigeo Kondo
  • Patent number: 9190659
    Abstract: A secondary battery that can avoid reduction in battery capacity over the lapse of charge-discharge cycles and can exhibit high performance is provided. The secondary battery includes a first electrode layer, a second electrode layer, and an electrolyte layer provided between the first and second electrode layers, the electrolyte layer including electrolyte particles, wherein at least one of the first and second electrode layers includes a base member having a major surface on which a plurality of concave portions are formed and an electrode material filled in at least the concave portions, the major surface facing to the electrolyte layer.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: November 17, 2015
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Shigeo Kondo, Yasumasa Takeuchi, Yoshiharu Ajiki
  • Publication number: 20150262693
    Abstract: A nonvolatile semiconductor memory device according to embodiment comprises: a memory cell array configured to include word lines and memory strings, the memory strings having memory cells connected in series, the memory cells being connected to the word lines; and a control unit configured to execute a read sequence to read data page-by-page, the control unit, during the read sequence on a first page, executing a read operation by applying a first read-pass voltage to a second word line and reading data in the first page, and executing a re-read operation by applying a second read-pass voltage different from the first read-pass voltage to the second word line and reading data in a first cell in a case where data read from a first cell group in the first page coincides with a specific first reference pattern.
    Type: Application
    Filed: March 9, 2015
    Publication date: September 17, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Shigeo KONDO