Patents by Inventor Shigeo Kondo

Shigeo Kondo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220231032
    Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 21, 2022
    Applicant: KIOXIA CORPORATION
    Inventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
  • Patent number: 11329060
    Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: May 10, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
  • Patent number: 10930660
    Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 23, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
  • Publication number: 20210005616
    Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 7, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
  • Publication number: 20200403000
    Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kaito SHIRAI, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
  • Patent number: 10861557
    Abstract: A semiconductor storage apparatus includes: a memory cell array provided with memory cells; a word line connected to each gate of the memory cells; bit lines connected respectively to ends of the memory cells; and a control circuit. The control circuit controls a word line driver and a sense amplifier circuit to perform a first programming pass for programming data of states each of which has a first threshold distribution width to the memory cells and a second programming pass for programming data of the states each of which has a second threshold distribution width narrower than the first threshold distribution width to the memory cells, the second programming pass being performed after the first programming pass, and the first programming pass includes at least one first verify operation and one or more additional program operations.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: December 8, 2020
    Assignee: Kioxia Corporation
    Inventor: Shigeo Kondo
  • Patent number: 10804290
    Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kaito Shirai, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
  • Publication number: 20200194078
    Abstract: A semiconductor storage apparatus includes: a memory cell array provided with memory cells; a word line connected to each gate of the memory cells; bit lines connected respectively to ends of the memory cells; and a control circuit. The control circuit controls a word line driver and a sense amplifier circuit to perform a first programming pass for programming data of states each of which has a first threshold distribution width to the memory cells and a second programming pass for programming data of the states each of which has a second threshold distribution width narrower than the first threshold distribution width to the memory cells, the second programming pass being performed after the first programming pass, and the first programming pass includes at least one first verify operation and one or more additional program operations.
    Type: Application
    Filed: December 12, 2019
    Publication date: June 18, 2020
    Applicant: Kioxia Corporation
    Inventor: Shigeo Kondo
  • Publication number: 20200185395
    Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
  • Patent number: 10608007
    Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 31, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
  • Patent number: 10510425
    Abstract: A word-line controller applies a voltage to a selected word-line. A bit-line controller applies voltages to bit-lines. A detector detects data of memory-cells. A write sequence of writing data in selected memory-cells connected to the selected word-line has at least one write-loop including a write operation of applying a plurality of write voltages with the word-line controller and the bit-line controller, and a verify operation of verifying with the detection circuit whether a threshold voltage of each of the selected memory-cells has reached a plurality of reference voltages for corresponding write data. The word-line controller and the bit-line controller select a write voltage corresponding to a threshold voltage of each of the selected memory-cells from among the write voltages with respect to each of the write-loops, and apply the selected write voltage to the selected memory-cell in a subsequent write operation.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 17, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Shigeo Kondo
  • Publication number: 20190341391
    Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
  • Patent number: 10431590
    Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: October 1, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
  • Patent number: 10395739
    Abstract: According to an embodiment, a semiconductor memory device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a word line driving circuit, a sense amplifier circuit, and a controller. The memory cell connected to the selected word line is written with data using a write sequence including a plurality of write loops each including a write operation of applying a write voltage to the selected word line by the word line driving circuit and a verify operation of detecting data of the memory cell by the sense amplifier circuit. The controller determines an (n+k)-th (where n is an integer not less than 1 and k is an integer not less than 2) verify operation based on comparison between an n-th verify operation and an (n+1)-th verify operation in the write sequence.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 27, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Shigeo Kondo
  • Patent number: 10360974
    Abstract: According to one embodiment, a semiconductor memory of an embodiment includes memory cells, a word line, bit lines, and a controller. The word line is coupled to a plurality of memory cells. The plurality of bit lines are respectively coupled to the plurality of memory cells. The controller executes a first write, and classifies a plurality of memory cells to which the second data should be written into a plurality of subgroups in accordance with a result of the first write, and after the classification, the controller executes a second write that includes a first program loop.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: July 23, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Shigeo Kondo
  • Publication number: 20190214405
    Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.
    Type: Application
    Filed: March 13, 2019
    Publication date: July 11, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kaito SHIRAI, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
  • Publication number: 20190088313
    Abstract: According to one embodiment, a semiconductor memory of an embodiment includes memory cells, a word line, bit lines, and a controller. The word line is coupled to a plurality of memory cells. The plurality of bit lines are respectively coupled to the plurality of memory cells. The controller executes a first write, and classifies a plurality of memory cells to which the second data should be written into a plurality of subgroups in accordance with a result of the first write, and after the classification, the controller executes a second write that includes a first program loop.
    Type: Application
    Filed: March 8, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Shigeo KONDO
  • Publication number: 20180277222
    Abstract: According to an embodiment, a semiconductor memory device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a word line driving circuit, a sense amplifier circuit, and a controller. The memory cell connected to the selected word line is written with data using a write sequence including a plurality of write loops each including a write operation of applying a write voltage to the selected word line by the word line driving circuit and a verify operation of detecting data of the memory cell by the sense amplifier circuit. The controller determines an (n+k)-th (where n is an integer not less than 1 and k is an integer not less than 2) verify operation based on comparison between an n-th verify operation and an (n+1)-th verify operation in the write sequence.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 27, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Shigeo KONDO
  • Publication number: 20180277231
    Abstract: A word-line controller applies a voltage to a selected word-line. A bit-line controller applies voltages to bit-lines. A detector detects data of memory-cells. A write sequence of writing data in selected memory-cells connected to the selected word-line has at least one write-loop including a write operation of applying a plurality of write voltages with the word-line controller and the bit-line controller, and a verify operation of verifying with the detection circuit whether a threshold voltage of each of the selected memory-cells has reached a plurality of reference voltages for corresponding write data. The word-line controller and the bit-line controller select a write voltage corresponding to a threshold voltage of each of the selected memory-cells from among the write voltages with respect to each of the write-loops, and apply the selected write voltage to the selected memory-cell in a subsequent write operation.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 27, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Shigeo KONDO
  • Patent number: 9985044
    Abstract: A semiconductor memory device according to an embodiment, includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: May 29, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku