Abstract: An electrophotographic member having an endless shape comprises: a substrate; and an elastic layer on an outer peripheral surface thereof. The elastic layer contains a silicone rubber and metal silicon fillers dispersed in the silicone rubber. An average of area ratios of the metal silicon fillers in respective first binarized images is 42% or less, and an average of area ratios of the metal silicon fillers in respective second binarized images is 42% or less. The elastic layer has ? of 1.30 W/(m·K) or more, where ? is a thermal conductivity of the elastic layer in a thickness direction thereof, and the elastic layer has pV of 9.0 LOG?·cm or more, where pV is a common logarithm value of a volume resistivity thereof.

Abstract: A fixing member includes a substrate having an endless shape; and an elastic layer on an outer peripheral surface of the substrate, the elastic layer containing a silicone rubber and fillers dispersed in the silicone rubber, a content of the fillers with respect to the elastic layer being 35 vol % or more and 50 vol % or less. The fillers includes at least a first filler and a second filler. The first filler is at least one selected from the group consisting of: magnesium oxide; and zinc oxide. The second filler is at least one selected from the group consisting of metal silicon and silicon carbide. A proportion of a sum of the first filler and the second filler to a total amount of the fillers in the elastic layer is 90 vol % or more. Further, the average of 6 sets of representative coefficient A is 1.4 or more.

Abstract: A fixing member including: a substrate; and an elastic layer arranged on the substrate, wherein the elastic layer contains a silicone rubber and metal silicon powder dispersed in the silicone rubber, wherein the elastic layer has an elastic modulus of 0.10 MPa or more and 0.40 MPa or less, and wherein the metal silicon powder has an aspect ratio of 1.4 or more and 2.5 or less, and a repose angle of 35° or more and 52° or less.

Abstract: A fixing member for electrophotography having an endless shape has a base layer having an endless shape, and an elastic layer on the outer circumferential surface of the base layer. The elastic layer includes a silicone rubber and a filler dispersed in the silicone rubber. The total amount of the filler compounded in the elastic layer is 30 vol % or less based on the total volume of the elastic layer. The elastic layer satisfies the relation of ?td>?md>?nd. ?td is a thermal conductivity of the elastic layer in the circumferential direction, ?nd is a thermal conductivity of the elastic layer in the thickness direction, and ?md, is a thermal conductivity of the elastic layer in the longitudinal direction. ?td is 2.0 W/(m·K) or more, and ?nd is 1.3 W/(m·K) or more.

Abstract: An intermediary transfer belt having surface resistivity ?s of 1×109 ?/square or more and volume resistivity ?v of 1×1012 ?·cm or less includes a thermoplastic resin material containing carbon black. The carbon black contained in the thermoplastic resin material has a weight ratio of 22.5-28.5 weight % and include first carbon black and second carbon black. The first carbon black of the carbon black contained in the thermoplastic resin material has a weight ratio of 50-90 weight % and dibutyl phthalate absorption of 93-127 ml/100 g, and the second carbon black of the carbon black contained in the thermoplastic resin material has a weight ratio of 10-50 weight % and dibutyl phthalate absorption of 36-79 ml/100 g.

Abstract: A fixing member for electrophotography having an endless shape has a base layer having an endless shape, and an elastic layer on the outer circumferential surface of the base layer. The elastic layer includes a silicone rubber and a filler dispersed in the silicone rubber. The total amount of the filler compounded in the elastic layer is 30 vol % or less based on the total volume of the elastic layer. The elastic layer satisfies the relation of ?td>?md>?nd. ?td is a thermal conductivity of the elastic layer in the circumferential direction, ?nd is a thermal conductivity of the elastic layer in the thickness direction, and ?md, is a thermal conductivity of the elastic layer in the longitudinal direction. ?td is 2.0 W/(m·K) or more, and ?nd is 1.3 W/(m·K) or more.

Abstract: An intermediary transfer belt having surface resistivity ?s of 1×109 ?/square or more and volume resistivity ?v of 1×1012 ?·cm or less includes a thermoplastic resin material containing carbon black. The carbon black contained in the thermoplastic resin material has a weight ratio of 22.5-28.5 weight % and include first carbon black and second carbon black. The first carbon black of the carbon black contained in the thermoplastic resin material has a weight ratio of 50-90 weight % and dibutyl phthalate absorption of 93-127 ml/100 g, and the second carbon black of the carbon black contained in the thermoplastic resin material has a weight ratio of 10-50 weight % and dibutyl phthalate absorption of 36-79 ml/100 g.

Abstract: Provided is an image forming method which prevents the temperatures of printing heads from exceeding a predetermined temperature. In this image forming method, its basic assignment is changed when any one of the temperatures detected by the respective temperature sensors exceeds the predetermined temperature (for example, 60° C.). Specifically, each time the forming of an image on a printing medium (for example, a label) is completed, the temperatures of the respective printing heads are detected with the respective temperature sensors. When any one of the temperatures thus detected exceeds 60° C., the association of raster line regions with ink ejection opening arrays (the association of rasters with the printing heads) under the basic assignment is shifted one-by-one.

Abstract: To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.

Abstract: A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the first

Abstract: To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.

Abstract: A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease.

Abstract: Attempts have been made to increase the number of pins of packages accompanying the trend toward fabricating integrated circuits highly densely and in smaller sizes. The present invention provides technology for improving reliability in fabricating packages of the surface-mounted type that have increased number of pins. That is, when the packages are mounted on the wiring substrate, the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength of solder at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as a fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material.

Abstract: A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the first

Abstract: A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease.

Abstract: The present invention discloses a suitable mounting of a wafer scale LSI (wafer scale integration) (WSI) in which a slit formed in a wafer is fit to a connector, a U-shaped reinforcing rubber member is disposed at the circumferential edge of the wafer, or a flexible adhesive is used for bonding a substrate formed with through-holes and a wafer, to provide a WSI mounting structure of high integration degree and high reliability. Furthermore, a method of efficient mounting by conducting the wiring of the wafer and the connection with the external terminal of the chip in one identical production step is disclosed.

Abstract: A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease.

Abstract: An electric component part has its lead terminals bent in thickness directions in a middle section thereof at least two positions so that a step section virtually in parallel to the bottom of a circuit substrate is formed with the intention of absorbing the external force applied to the part by chaging the shape of the lead terminals. Increase in the part layout area due to the formation of the horizontal step section can be avoided, when necessary, by shifting the terminal lead out position on the component part inward thereby to minimize the jetty dimensions.

Abstract: A method of fabricating semiconductor integrated circuit devices having a semiconductor region in a position separated by a predetermined distance from a dielectric isolating region provided on the surface of a semiconductor wafer, comprising the steps of forming a first mask to define the dielectric isolating region and semiconductor region, forming a second mask over the first mask so as to cover the region which is to become the semiconductor region, and removing the second mask after the dielectric isolating region has been formed by the first and second masks, to form the semiconductor region. The method thus permits the semiconductor region to be self-aligned with the dielectric isolating region.