Patents by Inventor Shigeo Kuroda

Shigeo Kuroda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10855168
    Abstract: Each arm circuit of a power conversion device includes a plurality of cascaded cell blocks and a plurality of bypass circuits connected in parallel to the respective cell blocks. Each cell block includes: a first connection node on a high potential side and a second connection node on a low potential side for connection to another cell block; and a plurality of converter cells cascaded between the first and second connection nodes, each converter cell containing an energy storage. The plurality of converter cells include at least one first converter cell of a full-bridge (or hybrid) configuration and at least one second converter cell of a half-bridge configuration.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: December 1, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Ryosuke Uda, Kenichi Kuroda, Masashi Kitayama, Yoshiyuki Kono, Shigeo Hayashi
  • Publication number: 20200019093
    Abstract: An intermediary transfer belt having surface resistivity ?s of 1×109 ?/square or more and volume resistivity ?v of 1×1012 ?·cm or less includes a thermoplastic resin material containing carbon black. The carbon black contained in the thermoplastic resin material has a weight ratio of 22.5-28.5 weight % and include first carbon black and second carbon black. The first carbon black of the carbon black contained in the thermoplastic resin material has a weight ratio of 50-90 weight % and dibutyl phthalate absorption of 93-127 ml/100 g, and the second carbon black of the carbon black contained in the thermoplastic resin material has a weight ratio of 10-50 weight % and dibutyl phthalate absorption of 36-79 ml/100 g.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 16, 2020
    Inventors: Ryosuke Tsuruga, Toshiyuki Yoshida, Jun Ohira, Akeshi Asaka, Hiroto Sugimoto, Takanori Ueno, Koji Sato, Midai Suzuki, Atsushi Hori, Kaoru Okamoto, Megumi Uchino, Kazuhisa Shirayama, Naoto Kameyama, Kiyonori Soutome, Shigeo Kuroda, Akira Okano, Hiroshi Tominaga
  • Publication number: 20090058916
    Abstract: Provided is an image forming method which prevents the temperatures of printing heads from exceeding a predetermined temperature. In this image forming method, its basic assignment is changed when any one of the temperatures detected by the respective temperature sensors exceeds the predetermined temperature (for example, 60° C.). Specifically, each time the forming of an image on a printing medium (for example, a label) is completed, the temperatures of the respective printing heads are detected with the respective temperature sensors. When any one of the temperatures thus detected exceeds 60° C., the association of raster line regions with ink ejection opening arrays (the association of rasters with the printing heads) under the basic assignment is shifted one-by-one.
    Type: Application
    Filed: August 25, 2008
    Publication date: March 5, 2009
    Applicant: CANON FINETECH INC.
    Inventor: Shigeo Kuroda
  • Patent number: 5309011
    Abstract: To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: May 3, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Tazunoki, Hiromitsu Mishimagi, Makoto Homma, Toshiyuki Sakuta, Hisashi Nakamura, Keiji Sasaki, Minoru Enomoto, Toshihiko Satoh, Kunizo Sahara, Shigeo Kuroda, Kanji Otsuka, Masao Kawamura, Hinoko Kurosawa, Kazuya Ito
  • Patent number: 5223454
    Abstract: A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the first
    Type: Grant
    Filed: September 17, 1991
    Date of Patent: June 29, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Uda, Tasuku Tanaka, Yoshiaki Emoto, Shigeo Kuroda
  • Patent number: 5191224
    Abstract: To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.
    Type: Grant
    Filed: December 13, 1990
    Date of Patent: March 2, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Tazunoki, Hiromitsu Mishimagi, Makoto Homma, Toshiyuki Sakuta, Hisashi Nakamura, Keiji Sasaki, Minoru Enomoto, Toshihiko Satoh, Kunizo Sahara, Shigeo Kuroda, Kanji Otsuka, Masao Kawamura, Hinoko Kurosawa, Kazuya Ito
  • Patent number: 5141888
    Abstract: A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease.
    Type: Grant
    Filed: January 18, 1991
    Date of Patent: August 25, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Mikinori Kawaji, Toshihiko Takakura, Akihisa Uchida, Shigeo Kuroda, Yoichi Tamaki, Takeo Shiba, Kazuhiko Sagara, Masao Kawamura
  • Patent number: 5067007
    Abstract: Attempts have been made to increase the number of pins of packages accompanying the trend toward fabricating integrated circuits highly densely and in smaller sizes. The present invention provides technology for improving reliability in fabricating packages of the surface-mounted type that have increased number of pins. That is, when the packages are mounted on the wiring substrate, the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength of solder at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as a fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material.
    Type: Grant
    Filed: January 24, 1991
    Date of Patent: November 19, 1991
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kanji Otsuka, Masao Kato, Takashi Kumagai, Mitsuo Usami, Shigeo Kuroda, Kunizo Sahara, Takeo Yamada, Seiji Miyamoto, Yuuji Shirai, Takayuki Okinaga, Kazutoshi Kubo, Hiroshi Tachi, Masayuki Kawashima
  • Patent number: 5049972
    Abstract: A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the first
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: September 17, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Uda, Tasuku Tanaka, Yoshiaki Emoto, Shigeo Kuroda
  • Patent number: 5011788
    Abstract: A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease.
    Type: Grant
    Filed: December 15, 1988
    Date of Patent: April 30, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Mikinori Kawaji, Toshihiko Takakura, Akihisa Uchida, Shigeo Kuroda, Yoichi Tamaki, Takeo Shiba, Kazuhiko Sagara, Masao Kawamura
  • Patent number: 4965653
    Abstract: The present invention discloses a suitable mounting of a wafer scale LSI (wafer scale integration) (WSI) in which a slit formed in a wafer is fit to a connector, a U-shaped reinforcing rubber member is disposed at the circumferential edge of the wafer, or a flexible adhesive is used for bonding a substrate formed with through-holes and a wafer, to provide a WSI mounting structure of high integration degree and high reliability. Furthermore, a method of efficient mounting by conducting the wiring of the wafer and the connection with the external terminal of the chip in one identical production step is disclosed.
    Type: Grant
    Filed: February 28, 1990
    Date of Patent: October 23, 1990
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kanji Otsuka, Shigeo Kuroda, Katsuyuki Sato, Hisashi Nakamura, Shinichi Shouji
  • Patent number: 4819054
    Abstract: A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease.
    Type: Grant
    Filed: February 6, 1987
    Date of Patent: April 4, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Mikinori Kawaji, Toshihiko Takakura, Akihisa Uchida, Shigeo Kuroda, Yoichi Tamaki, Takeo Shiba, Kazuhiko Sagara, Masao Kawamura
  • Patent number: 4739125
    Abstract: An electric component part has its lead terminals bent in thickness directions in a middle section thereof at least two positions so that a step section virtually in parallel to the bottom of a circuit substrate is formed with the intention of absorbing the external force applied to the part by chaging the shape of the lead terminals. Increase in the part layout area due to the formation of the horizontal step section can be avoided, when necessary, by shifting the terminal lead out position on the component part inward thereby to minimize the jetty dimensions.
    Type: Grant
    Filed: September 15, 1986
    Date of Patent: April 19, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Watanabe, Fumiyuki Kobayashi, Masao Sekibata, Shigeo Kuroda, Akio Yasukawa, Shigejiro Sekine
  • Patent number: 4469535
    Abstract: A method of fabricating semiconductor integrated circuit devices having a semiconductor region in a position separated by a predetermined distance from a dielectric isolating region provided on the surface of a semiconductor wafer, comprising the steps of forming a first mask to define the dielectric isolating region and semiconductor region, forming a second mask over the first mask so as to cover the region which is to become the semiconductor region, and removing the second mask after the dielectric isolating region has been formed by the first and second masks, to form the semiconductor region. The method thus permits the semiconductor region to be self-aligned with the dielectric isolating region.
    Type: Grant
    Filed: January 11, 1983
    Date of Patent: September 4, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Shigeo Kuroda, Takahiko Takahashi, Akio Anzai