Abstract: A data processor has a plurality of vector registers capable of reading and writing in parallel; a plurality of ALU's; a plurality of sending circuits, one for each of said vector registers, each for updating a read address for the corresponding vector register requested by a succeeding instruction within such a limit that said read address does not pass a write address for said corresponding vector register requested by a preceding instruction and sending out a read data together with a data valid signal for each updating; circuits for sending the data and the data valid signals from said plurality of sending circuits to the ALU's requested by the corresponding instructions; and circuits, one for each of said ALU's, each for controlling the corresponding ALU such that when the data valid signals have been received from all of the vector registers necessary to execute the instruction which uses the corresponding ALU, the corresponding ALU operates on the data supplied with said data valid signals and sends ou

Abstract: A vector processor comprises a main storage for storing scalar instruction chains and vector instruction chains for executing desired operations, and a scalar processing unit and a vector processing unit for separately fetching the scalar instruction chains and the vector instruction chains, decoding them and executing them so that the scalar processing and the vector processing are carried out in overlap.

Abstract: In an operation unit wherein a series of data is sequentially applied, a predetermined operation is performed in synchronism with the input data in a pipelined manner, and the predetermined operation is applied to an input data and the result of the predetermined operation for a preceding input data. There are provided a plurality of partial operation devices which respectively compute a plurality of different partial data of a result data to be obtained as a result of the predetermined operation, and when one of the partial data is obtained, the one partial data is immediately used for the operation for the subsequent input data. Consequently, the operation for the subsequent input data can be started before the operation for the remainder of the partial data of the preceding input data is completed.

Abstract: An approximate quotient-correcting circuit wherein an approximate quotient Q.sub.H, a divisor D, and the least significant bit of the fraction part of a dividend N are read out; the approximate quotient Q.sub.H and the divisor D are multiplied; it is decided whether the lower m digits of Q.sub.H .times.D are not all `0` and whether the m-th significant bit of Q.sub.H .times.D is coincident with the m-th significant bit of N; and when the result of the decision is positive, Q.sub.H -2.sup.-m is provided as a quotient.

Abstract: A FIFO memory comprises a plurality of readable and writable data banks, a mode indicating circuit for indicating a write mode to a plurality of data banks repetitively, and a read/write control circuit for writing received data to the data bank to which the write mode has been indicated and reading the data from the data banks to which the write mode is not indicated.

Abstract: A gathering system in an electronic computer including detecting means for detecting the occurrences of each of a plurality of events, a counter group having a plurality of counters each of which counts the number of occurrences of corresponding event until the number thereof becomes 2.sup.l, a storage having a plurality of memory areas, each storing 2.sup.K.multidot.l occurrences of the corresponding event and a processing unit for gathering data representative of the number of occurrences of each of the events from the counter and the storage unit.

Abstract: In a virtual memory system capable of embodying therein multiple virtual spaces used in a switching mode and having a high speed memory for storing address sets each including a virtual address of the virtual space and a real address of a real space corresponding to the virtual address and indicators for setting the validity or invalidity state of the corresponding address sets, a switching system such that when the multiple virtual spaces are switched, the virtual address in the addressed address set is compared with a special address stored in a register by a comparator, and the indicator corresponding to the addressed address set is set to the invalidity state when the result of comparison fulfills a predetermined condition.