Abstract: In a semiconductor memory having a column-direction serial access function, two systems of circuits for selecting and fetching data are provided. A circuit operation is alternately performed such that one system is set up while the other system is accessed, thereby reducing a cycle time for a data selecting/fetching operation.

Abstract: The disclosed semiconductor memory comprises a random access memory port, a serial access memory port, a data transfer gate formed between the two ports, and in particular a test signal generating circuit for generating a test signal to the data transfer gate to close the gate so that data stored in the serial access memory port can be read to outside, without transferring data from the random access memory port to the serial access memory port. Therefore, it is possible to discriminate an erroneous operation caused when data are read from the serial access memory port from that caused when data are transferred from the random access memory port to the serial access memory port.

Abstract: A semiconductor memory device comprises a memory cell array, a row decoder, a column decoder, registers and a control unit. The control unit allows the write operational mode of the column decoder to switch. In the ordinary write operational mode, data in the n registers are written into the active memory cells of the n memory cell columns in on column block selected by the column decoder, respectively. In the block write mode, data in the n registers are written into active memory cells of the n memory cell columns in the 2.sup.N column blocks selected by the column decoder, respectively. Another semiconductor memory device comprises N memory units. Each memory unit comprises a memory cell array, a row decoder, a first column decoder, a second column decoder, a data input terminal, registers and a control circuit. The control circuit is operative to allow the operational mode.

Abstract: A multiport memory has a RAM port including a memory cell array having a plurality of memory cells arranged in a matrix form, sense amplifier circuit for sensing potential of a bit line after the storage potential has been transferred from the memory cells, restore circuit connected to the bit line for pulling up the potential of the bit line at the predetermined timing after sense operation has been started and a barrier circuit connected between the bit line and the sense amplifier circuit; and a SAM port including a data register, transfer gate and functional means for transferring serial data in the column direction. In this memory, the RAM port is connected to the SAM port by the transfer gate with the bit line directly connected to the data register, and the potentials at the bit line are amplified by the sense amplifier circuit and are directly transferred to the data register.

Abstract: There is disclosed a semiconductor integrated circuit device comprising: an external input signal lead provided outside a semiconductor chip; a power supply lead provided outside the semiconductor chip; a first electrode connected to an internal circuit on the semiconductor chip, and arranged close to the external input signal lead, wherein when the circuit is caused to be operative, the first electrode is connected to the external input signal lead; and a second electrode connected to the first electrode on the semiconductor chip, and arranged close to said power supply lead, wherein when the circuit is not caused to be operative, the second electrode is connected to the power supply lead. This invention is applicable to the device wherein there are provided a plurality of internal circuits.

Abstract: In a semiconductor memory system of the serial column access type, a redundant column is used for replacing a defective column. Redundant data lines are connected to the redundant column through a redundant column selection gate. A defective address detection circuit detects the address of a defective column to enable the redundant column selection gate. An address counter is provided for a defective address detection circuit. A redundant column selection circuit selects the redundant column in response to a detection signal from the defective address detection circuit. A data line switching circuit switches, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines to the redundant data lines. With this circuit arrangement, in a redundant column select mode, the regular data lines are separated from the data input/output drive circuit.

Abstract: A function selection circuit includes a first signal generating circuit for generating a plurality of first signals corresponding to each of all combinations of a plurality of input signal states; and a second signal generating circuit for selecting a plurality of logical sums of combinations of the plurality of first signals and generating a second signal corresponding to each of the plurality of logical sums which selectively activates an operation function indicated by a truth table.

Abstract: A semiconductor memory device is disclosed which comprises, as shown in FIG. 1, a pair of column lines, memory cells connected to the corresponding column lines, a sense amplifier connected to the column lines, row lines for selecting the memory cells in accordance with a row address signal, and first and second transistors having their current paths connected between the column lines and a fixed potential supply terminal supplied with a positive power source potential or a ground potential, wherein the gates of the first and second transistors are connected to the first and second row lines for a data rewrite operation which can be selected independently of the row line.

Abstract: Memory cells disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by a first gate. One memory cell column in the n memory cell colunns in a selected block is selected by a second gate. One memory cell in a selected memory cell column is selected by a row address. The data in a selected memory cell are stored in a register and output therefrom.

Abstract: This invention provides a multiport memory including a storage section A having bit lines BL and BL, a word line WL, a data transfer gate .phi.DT, and a dynamic memory cell Cs, and a serial port B having a serial access function in a column direction of the storage section, wherein the memory includes a circuit for disabling a word line signal WL for selecting one word line under the conditions that a row address strobe signal RAS is raised in a transfer cycle in which data held by the memory cell is transferred to the serial port, and that the data transfer to the serial port is completed by the data transfer gate .phi.DT.

Abstract: A semiconductor device is provided with a first protection path between a first terminal and an input terminal, a second protection path between a second power source terminal and the input terminal, and a third protection path between the first and the second power source terminals. Each protection path includes a first and a second P-N junction formed to be reverse biased, and is made conductive when the voltage between the corresponding two terminals exceeds a predetermined voltage so as to protect an internal circuit connected to the input terminal from an electrostatic breakdown.

Abstract: A data transfer circuit is connected between first and second circuits so as to control data transfers therebetween. The data transfer circuit comprises first and second latch circuits for latching data in response to first and second latch control signals, respectively, a first data transfer gate connected between the first circuit and the first latch circuit and responsive to a first gate control signal to make electrical connection or disconnection therebetween, a second transfer gate connected between the first and second data latch circuits and responsive to a second gate control signal to make electrical connection or disconnection therebetween, and a third data transfer gate connected between the second data latch circuit and the second circuit and responsive to a third gate control signal to make electrical connection or disconnection therebetween.

Abstract: A signal externally supplied to determine the operation mode is supplied to a first buffer circuit. A CAS signal is supplied to a second buffer circuit. The signals whose levels are converted by the first and second buffer circuits are supplied to a mode selection circuit. The operation of the mode selection circuit is controlled by a RAS signal, and it latches and outputs a mode selection signal based on the outputs of the first and second buffer circuits. An externally supplied address signal and an address signal formed in the device are supplied to address buffer circuit. The address buffer circuit selects one of the received address signals based on the RAS signal anad the mode selection signal output from the mode selection circuit. A selected one of the address signals is supplied to a word line selection/driving circuit. When a mode other than the auto-refresh mode is specified, the mode setting signal is set up before the RAS signal is activated.

Abstract: For a semiconductor integrated circuit having a data output buffer, separate power source pads and separate reference pads are provided for the data output buffer and the circuit components. Thus, any potential fluctuations or noise generated in the data output buffer are not transmitted to the circuit components, resulting in decreased circuit malfunction.

Abstract: An integrated circuit includes an input buffer circuit and an output buffer circuit. The source voltage to the input buffer circuit and the output buffer circuit are supplied through bonding pads formed independently on a semiconductor chip, and electrically connected to a source potential lead pin. The input node of the input buffer circuit is coupled to the source potential of the output buffer circuit with a capacitor.

Abstract: A semiconductor memory device determines the level of a select control signal, according to the level of drive signals for two systems as generated in the preceding access cycle, and the level of the least significant bit of an address to fetch data in a desired serial access cycle. In accordance with this select signal, a select circuit selects one of the drive signals as generated by drive signal generating circuits, and supplies the selected signal to two data selecting/fetching systems. The function of this select circuit allows one of the two data selecting/fetching systems to first start the data access operation.

Abstract: In this invention, in a sensing circuit of a dynamic memory, barrier transistors are provided between the bit lines and the sensing amplifier. A circuit is provided that, on sensing and on data transfer, changes the gate potential of the barrier transistors so that during the sensing operation the barrier transistors are temporarily turned OFF, so that sensing can be carried out with high sensitivity, as the sensing system is not affected by the parasitic capacitance of the bit lines, while, on data transfer to the input/output lines, the gate potential of the barrier transistors is raised to a level greater than a value reached by adding the threshold value of the MOS transistors to the power source voltage, so that the conductance of the barrier transistors is increased, thereby speeding up the presensing of the input/output lines in the sensing circuit.

Abstract: A flip-flop circuit has a power terminal set at 5 V, first and second output terminals, a latch section for charging one of the first and second terminals to 5 V and discharging the other one of the first and second terminals to 0 V in accordance with an input signal, a first MOS transistor having a current path connected between the power and first output terminals, a second MOS transistor for charging the gate of the first MOS transistor while the potential of the second output terminal is changed from 5 V to 0 V, and a capacitor for bootstrapping the gate potential of the first MOS transistor to turn on the first MOS transistor.