Patents by Inventor Shigeo Oshiro
Shigeo Oshiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10658207Abstract: Techniques for reducing particle contamination on a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a platen having different regions, where the pressure levels in the regions may be substantially equal. For example, the platen may comprise a platen body comprising first and second recesses, the first recess defining a fluid region for holding fluid for maintaining a temperature of the substrate at a desired temperature, the second recess defining a first cavity for holding a ground circuit; a first via defined in the platen body, the first via having first and second openings, the first opening proximate to the fluid region and the second opening proximate to the first cavity, wherein pressure level of the fluid region may be maintained at a level that is substantially equal to pressure level of the first cavity.Type: GrantFiled: April 16, 2018Date of Patent: May 19, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: David E. Suuronen, Dale K. Stone, Shigeo Oshiro, Arthur P. Riaf, Edward D. MacIntosh
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Publication number: 20180233386Abstract: Techniques for reducing particle contamination on a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a platen having different regions, where the pressure levels in the regions may be substantially equal. For example, the platen may comprise a platen body comprising first and second recesses, the first recess defining a fluid region for holding fluid for maintaining a temperature of the substrate at a desired temperature, the second recess defining a first cavity for holding a ground circuit; a first via defined in the platen body, the first via having first and second openings, the first opening proximate to the fluid region and the second opening proximate to the first cavity, wherein pressure level of the fluid region may be maintained at a level that is substantially equal to pressure level of the first cavity.Type: ApplicationFiled: April 16, 2018Publication date: August 16, 2018Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: David E. Suuronen, Dale K. Stone, Shigeo Oshiro, Arthur P. Riaf, Edward D. MacIntosh
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Patent number: 9953849Abstract: Techniques for reducing particle contamination on a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a platen having different regions, where the pressure levels in the regions may be substantially equal. For example, the platen may comprise a platen body comprising first and second recesses, the first recess defining a fluid region for holding fluid for maintaining a temperature of the substrate at a desired temperature, the second recess defining a first cavity for holding a ground circuit; a first via defined in the platen body, the first via having first and second openings, the first opening proximate to the fluid region and the second opening proximate to the first cavity, wherein pressure level of the fluid region may be maintained at a level that is substantially equal to pressure level of the first cavity.Type: GrantFiled: March 25, 2014Date of Patent: April 24, 2018Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: David E. Suuronen, Dale K. Stone, Shigeo Oshiro, Arthur P. Riaf, Edward D. MacIntosh
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Publication number: 20150279704Abstract: Techniques for reducing particle contamination on a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a platen having different regions, where the pressure levels in the regions may be substantially equal. For example, the platen may comprise a platen body comprising first and second recesses, the first recess defining a fluid region for holding fluid for maintaining a temperature of the substrate at a desired temperature, the second recess defining a first cavity for holding a ground circuit; a first via defined in the platen body, the first via having first and second openings, the first opening proximate to the fluid region and the second opening proximate to the first cavity, wherein pressure level of the fluid region may be maintained at a level that is substantially equal to pressure level of the first cavity.Type: ApplicationFiled: March 25, 2014Publication date: October 1, 2015Inventors: David E. Suuronen, Dale K. Stone, Shigeo Oshiro, Arthur P. Riaf, Edward D. MacIntosh
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Patent number: 9082804Abstract: An electrostatic clamp which more effectively removes built up charge from a substrate prior to removal is disclosed. Currently, the lift pins and the ground pins are the only mechanism used to remove charge from the substrate after implantation. The present discloses describes an electrostatic chuck in which the top dielectric surface has an embedded conductive region, such as a ring shaped conductive region in the sealing ring. Thus, regardless of the orientation of the substrate during release, at least a portion of the substrate will contain the conductive region on the dielectric layer of the workpiece support. This conductive region may be connected to ground through the use of conductive vias in the dielectric layer. In some embodiments, these conductive vias are the fluid conduits used to supply gas to the back side of the substrate.Type: GrantFiled: February 7, 2011Date of Patent: July 14, 2015Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Julian Blake, Dale K. Stone, Lyudmila Stone, David Suuronen, Shigeo Oshiro
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Patent number: 8681472Abstract: Techniques for reducing particle contamination on a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a ground pin that extends two regions of a platen that support the substrate. The ground pin may comprise a pin body; and a sleeve comprising an upper portion, a side portion, and a lower portion, the sleeve being configured to fit around the pin body, the sleeve including a fluid channel configured to transport fluid between the upper portion and the lower portion of the sleeve.Type: GrantFiled: June 18, 2009Date of Patent: March 25, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: David E. Suuronen, Dale K. Stone, Shigeo Oshiro, Arthur P. Riaf, Edward D. MacIntosh
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Publication number: 20120200980Abstract: An electrostatic clamp which more effectively removes built up charge from a substrate prior to removal is disclosed. Currently, the lift pins and the ground pins are the only mechanism used to remove charge from the substrate after implantation. The present discloses describes an electrostatic chuck in which the top dielectric surface has an embedded conductive region, such as a ring shaped conductive region in the sealing ring. Thus, regardless of the orientation of the substrate during release, at least a portion of the substrate will contain the conductive region on the dielectric layer of the workpiece support. This conductive region may be connected to ground through the use of conductive vias in the dielectric layer. In some embodiments, these conductive vias are the fluid conduits used to supply gas to the back side of the substrate.Type: ApplicationFiled: February 7, 2011Publication date: August 9, 2012Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Julian Blake, Dale K. Stone, Lyudmila Stone, David Suuronen, Shigeo Oshiro
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Publication number: 20090317964Abstract: Techniques for reducing particle contamination on a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a platen having different regions, where the pressure levels in the regions may be substantially equal. For example, the platen may comprise a platen body comprising first and second recesses, the first recess defining a fluid region for holding fluid for maintaining a temperature of the substrate at a desired temperature, the second recess defining a first cavity for holding a ground circuit; a first via defined in the platen body, the first via having first and second openings, the first opening proximate to the fluid region and the second opening proximate to the first cavity, wherein pressure level of the fluid region may be maintained at a level that is substantially equal to pressure level of the first cavity.Type: ApplicationFiled: June 18, 2009Publication date: December 24, 2009Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: David E. SUURONEN, Dale K. Stone, Shigeo Oshiro, Arthur P. Riaf, Edward D. MacIntosh