Patents by Inventor Shigeru Atsumi

Shigeru Atsumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7283405
    Abstract: A semiconductor memory device able to read out data at a high speed continuously, provided with, corresponding to a plurality of banks, current address registers for holding addresses for reading data of cell arrays, reserved address registers able to receive in advance and hold reserved addresses for next read operations from the outside, and bank control circuits for making the current address registers hold reserved addresses held in the reserved address registers, making the data be read out, and making the data latch circuits hold the data when the data read out from the cell arrays of the banks by addresses held in the current address registers and held in the data latch circuits become able to be transferred to the outside, and a signal processing system relating to the same.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: October 16, 2007
    Assignee: Sony Corporation
    Inventors: Hidetoshi Yamanaka, Toshiyuki Nishimura, Shigeru Atsumi, Daisuke Yoshioka
  • Patent number: 7203120
    Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: April 10, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
  • Patent number: 7180796
    Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: February 20, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
  • Patent number: 7120053
    Abstract: A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a direction of the main cell word lines.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: October 10, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeru Atsumi, Masao Kuriyama, Akira Umezawa, Hironori Banba, Tadayuki Taura, Hidetoshi Saito
  • Publication number: 20060055453
    Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
    Type: Application
    Filed: November 9, 2005
    Publication date: March 16, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
  • Publication number: 20060055452
    Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
    Type: Application
    Filed: November 9, 2005
    Publication date: March 16, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
  • Patent number: 7002203
    Abstract: A semiconductor device at least has a memory cell array. The memory cell array has active regions extending linearly in parallel with one another at predetermined intervals and each containing alternating source and drain regions, gate electrodes orthogonally crossing the active regions between the source and drain regions and each having a floating gate and a control gate laid one upon another, first conductors extending linearly in parallel with the gate electrodes and connected to corresponding ones of the source regions through source contacts, and second conductors connected to corresponding ones of the drain regions through drain contacts.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: February 21, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Mori, Shigeru Atsumi
  • Patent number: 6999365
    Abstract: A semiconductor memory device is provided using a sense amp circuitry capable of lowering a supply voltage. The semiconductor memory device includes an array of memory cells each configured to store data in accordance with the presence/absence or the magnitude of a current; a sense amp configured to compare a voltage caused on a sense line based on data in a memory cell selected from the array of memory cells with a reference voltage applied to a reference sense line to determine the data; and a reference voltage generator configured to generate the reference voltage applied to the reference sense line.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: February 14, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Takano, Shigeru Atsumi, Toru Tanzawa
  • Patent number: 6996024
    Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: February 7, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
  • Patent number: 6972446
    Abstract: A number of transistors including gate oxide films of different thicknesses and an external terminal are formed on a semiconductor substrate. The transistor connected directly to the external terminal is a transistor other than the transistor having the thinnest gate oxide film. That is, a node which is in contact with an external power supply and thus requires a high breakdown voltage is formed of a thick gate oxide film transistor, while a node which is not in contact with the external power supply is formed of a thin gate oxide film transistor. With this structure, a number of transistors including gate oxide films of different thicknesses can be integrated in a single chip without deterioration of the transistor characteristics. Hence, the degree of freedom with which to design devices/circuits can be remarkably enhanced.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: December 6, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeru Atsumi
  • Publication number: 20050259479
    Abstract: A semiconductor memory device able to read out data at a high speed continuously, provided with, corresponding to a plurality of banks, current address registers for holding addresses for reading data of cell arrays, reserved address registers able to receive in advance and hold reserved addresses for next read operations from the outside, and bank control circuits for making the current address registers hold reserved addresses held in the reserved address registers, making the data be read out, and making the data latch circuits hold the data when the data read out from the cell arrays of the banks by addresses held in the current address registers and held in the data latch circuits become able to be transferred to the outside, and a signal processing system relating to the same.
    Type: Application
    Filed: May 11, 2005
    Publication date: November 24, 2005
    Applicant: Sony Corporation
    Inventors: Hidetoshi Yamanaka, Toshiyuki Nishihara, Shigeru Atsumi, Daisuke Yoshioka
  • Publication number: 20050117406
    Abstract: A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a direction of the main cell word lines.
    Type: Application
    Filed: January 12, 2005
    Publication date: June 2, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeru Atsumi, Masao Kuriyama, Akira Umezawa, Hironori Banba, Tadayuki Taura, Hidetoshi Saito
  • Publication number: 20050111269
    Abstract: A semiconductor device at least has a memory cell array. The memory cell array has active regions extending linearly in parallel with one another at predetermined intervals and each containing alternating source and drain regions, gate electrodes orthogonally crossing the active regions between the source and drain regions and each having a floating gate and a control gate laid one upon another, first conductors extending linearly in parallel with the gate electrodes and connected to corresponding ones of the source regions through source contacts, and second conductors connected to corresponding ones of the drain regions through drain contacts.
    Type: Application
    Filed: September 15, 2003
    Publication date: May 26, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiichi Mori, Shigeru Atsumi
  • Patent number: 6888764
    Abstract: A semiconductor device has an address counter to output, in a first mode, a first block address whereas, in a second mode, a second block address selected from a block-address space two times larger than a block-address space corresponding to memory blocks, the memory blocks and at least one redundant block being included in a memory section, and a block-selection controller, in the second mode, one of the memory blocks, which corresponds to the output of the address counter, when the most significant value of the second block address as the output of the address counter is at a first level whereas select the redundant block while the memory blocks are inhibited from selection, when the most significant value is at a second level.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: May 3, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Shiga, Tadayuki Taura, Shigeru Atsumi
  • Patent number: 6865125
    Abstract: A non-volatile semiconductor memory comprises a memory cell array having a plurality of non-volatile memory cells, at least one reference cell, a read circuit for reading data by applying a first voltage to one of word lines to compare a current flowing through one of bit lines with a current flowing through the reference cell, an erase circuit for erasing the data by applying a voltage to at least two selected from the word lines, the bit lines, the source lines and a semiconductor region including the memory cells, first and second regulators, and an erase verify circuit for detecting whether the erase has finished by applying an output voltage of the first regulator to word lines of the memory cells to be erased, while applying an output voltage of the second regulator to a word line of the reference cell, thereby comparing a cell current of selected one of the memory cells with a cell current of the reference cell.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: March 8, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Tanzawa, Shigeru Atsumi
  • Patent number: 6856543
    Abstract: A semiconductor integrated circuit device includes fuse cells arranged at a fuse cell array, a fuse cell data program and erase circuit, a fuse cell data control circuit, and fuse data latch circuits. The fuse cells include erasable and programmable nonvolatile memory cells. The fuse cell data program and erase circuit programs fuse data to the memory cells and erases the fuse data from the memory cells. The fuse cell data control circuit controls read out timing of the fuse data stored in the memory cells based on a signal generated upon detection of power-on. The fuse data latch circuits latch the fuse data read out from the memory cells.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: February 15, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeru Atsumi, Masao Kuriyama, Akira Umezawa, Hironori Banba, Tadayuki Taura, Hidetoshi Saito
  • Patent number: 6850437
    Abstract: A nonvolatile semiconductor memory device includes a first memory cell array including electrically re-programmable main memory cells, a second memory cell array including electrically data-programmable redundancy memory cells, a first storage configured to store a specified code, a first comparator configured to compare a selected code with the specified code to generate an activating signal, a faulty address latch circuit configured to be activated by the activating signal and controlled to temporarily latch a fault address corresponding to the fault, a second storage configured to store the faulty address latched by the faulty address latch circuit, a second comparator configured to compare an input address with the faulty address to generate a replacement control signal when the input address coincides with the faulty address, and a replacing circuit configured to replace an output of the first memory cell array with an output of the second memory cell array.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: February 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadayuki Taura, Shigeru Atsumi, Toru Tanzawa
  • Publication number: 20050002252
    Abstract: A semiconductor memory device comprises memory cell array, a sense amp, and a reference voltage generator. The reference voltage generator includes a reference cell unit containing a reference cell to flow a reference current and a first current source load to supply a current to the reference cell; a reference transistor unit containing a reference transistor to flow a current reflecting the reference current and a second current source load to supply a current to the reference transistor; a control amp for negative feedback control of the reference transistor; a current source transistor; and a third current source load connected to a reference sense line.
    Type: Application
    Filed: July 22, 2004
    Publication date: January 6, 2005
    Inventors: Yoshinori Takano, Shigeru Atsumi, Toru Tanzawa
  • Publication number: 20040264271
    Abstract: A non-volatile semiconductor memory comprises a memory cell array having a plurality of non-volatile memory cells, at least one reference cell, a read circuit for reading data by applying a first voltage to one of word lines to compare a current flowing through one of bit lines with a current flowing through the reference cell, an erase circuit for erasing the data by applying a voltage to at least two selected from the word lines, the bit lines, the source lines and a semiconductor region including the memory cells, first and second regulators, and an erase verify circuit for detecting whether the erase has finished by applying an output voltage of the first regulator to word lines of the memory cells to be erased, while applying an output voltage of the second regulator to a word line of the reference cell, thereby comparing a cell current of selected one of the memory cells with a cell current of the reference cell.
    Type: Application
    Filed: July 16, 2004
    Publication date: December 30, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toru Tanzawa, Shigeru Atsumi
  • Publication number: 20040252552
    Abstract: A first address subset is allocated as a first column address in a nonvolatile semiconductor memory. In addition, a second address subset higher in order than the first address subset is allocated as a first row address. Furthermore, a third address subset higher in order than the second address subset is allocated as a second column address.
    Type: Application
    Filed: July 9, 2004
    Publication date: December 16, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toru Tanzawa, Shigeru Atsumi