Abstract: A standard mass chromatogram which a substance to be detected exhibits is provided as a database within an apparatus. A measured mass chromatogram obtained by measurement and the standard mass chromatogram stored in the database are compared with each other after their standardization to determine the degree of coincidence of the two. Then, by utilizing the degree of coincidence, it is determined whether the substance to be detected has been detected or not. Further, two ions are selected from among plural ions derived from the substance to be detected and correlation between mass chromatograms of the two selected ions is compared with correlation between mass chromatograms of the two selected ions stored in the database to determine the degree of coincidence of the two. This degree of coincidence is also utilized for determining whether the substance to be detected has been detected or not.

Abstract: An object of the present invention is to obtain an apparatus and a method for the detection of chemical agents which are suitable for detecting sulfur mustard and lewisite 1 and are satisfactory from the viewpoint of the speed of detection of chemical agents, the reduction of the rate of wrong information, the specification of the kinds of the chemical agents, and an unmanned continuous-monitoring apparatus. In the present invention, the detecting apparatus comprises a sample introduction section 1 into which a sample is introduced to be heated, an ionization section 2 in which the sample from the sample introduction section is ionized, a mass spectrometry section 3, and a computer 6 for data analysis. When predetermined signals characteristic of sulfur mustard or lewisite 1 are observed, it becomes possible to specify the sample.

Abstract: An apparatus for detecting a chemical agent, capable of increasing a detection speed of a chemical agent, decreasing a false alarm rate, pinning down the kind of a chemical agent, and meeting specifications for unattended continuous monitoring equipment suitable for detecting sarin or soman. This detection apparatus comprises a sample introduction unit for introducing a sample, an ionizing unit for positively ionizing the sample from the sample introduction unit, a mass spectrometer unit for analyzing ions of the sample, and a computer for analyzing data, and is best suited for identifying a dangerous substance by detecting signals peculiar to chemical agents, such as sarin or soman.

Abstract: An object of the present invention is to obtain an apparatus and a method for the detection of chemical agents which are suitable for detecting sulfur mustard and lewisite 1 and are satisfactory from the viewpoint of the speed of detection of chemical agents, the reduction of the rate of wrong information, the specification of the kinds of the chemical agents, and an unmanned continuous-monitoring apparatus. In the present invention, the detecting apparatus comprises a sample introduction section 1 into which a sample is introduced to be heated, an ionization section 2 in which the sample from the sample introduction section is ionized, a mass spectrometry section 3, and a computer 6 for data analysis. When predetermined signals characteristic of sulfur mustard or lewisite 1 are observed, it becomes possible to specify the sample.

Abstract: An apparatus for detecting a chemical agent, capable of increasing a detection speed of a chemical agent, decreasing a false alarm rate, pinning down the kind of a chemical agent, and meeting specifications for unattended continuous monitoring equipment suitable for detecting sarin or soman. This detection apparatus comprises a sample introduction unit for introducing a sample, an ionizing unit for positively ionizing the sample from the sample introduction unit, a mass spectrometer unit for analyzing ions of the sample, and a computer for analyzing data, and is best suited for identifying a dangerous substance by detecting signals peculiar to chemical agents, such as sarin or soman.

Abstract: A memory matrix--which comprises memory cells arranged in matrix, each made up of a ferroelectric capacitor and an address selection MOSFET--is divided for each word line into a plurality of memory blocks. Each of the memory blocks is provided with a mode storage circuit that stores a DRAM mode (volatile mode) or an NV mode (non-volatile mode) in one-to-one correspondence for each memory block, and with a refresh operation count circuit that counts for each memory block the number of times the refresh operations is performed consecutively. During an n-th refresh operation (where n is a predetermined number of times), a memory access is made to temporarily change the plate voltage of the ferroelectric capacitor from one voltage to another and at the same time the mode storage circuit is changed from the DRAM mode to the NV mode. When a read or write operation to and from a memory cell in the memory block is performed, the mode storage circuit is changed from the NV mode to the DRAM mode.

Abstract: A memory matrix--which comprises memory cells arranged in matrix, each made up of a ferroelectric capacitor and an address selection MOSFET--is divided for each word line into a plurality of memory blocks. Each of the memory blocks is provided with a mode storage circuit that stores a DRAM mode (volatile mode) or NV mode (non-volatile mode) in one-to-one correspondence for each memory block, and with a refresh operation count circuit that counts for each memory block the number of times the refresh operations is performed consecutively. During an n-th refresh operation (where n is a predetermined number of times), a memory access is made to temporarily change the plate voltage of the ferroelectric capacitor from one voltage to another and at the same time the mode storage circuit is changed from the DRAM mode to the NV mode. When a read or write operation to and from a memory cell in the memory block is performed, the mode storage circuit is changed from the NV mode to the DRAM mode.

Abstract: Herein disclosed is a semiconductor integrated circuit device which has a memory array or a memory mat formed of memory cells arranged regularly in a matrix shape. At the end portion or inside of the memory array or memory cell in the region of the device where the patterning of the memory cells is discontinued or interrupted, the shape of an element isolating insulating film, which is formed for regulating the memory cells having pattern interruptions, is made substantially identical to the shape of the element isolating insulating film for regulating the memory cells in the region of the device where the patternings of the memory cells are of an uninterrupted regular form. In the location on the chip front face where the regular patterns associated with the memory area are discontinued, there is formed a dummy pattern having a shape made substantially identical to that of a gate electrode arranged at the end portion of the location where the regular patterns are interrupted.

Abstract: In a semiconductor memory, a latch circuit is arranged between the outputs of a sense amplifier and the inputs of a data output buffer. First pass-gates are arranged between the outputs of the sense amplifier and the latch circuit, while second pass-gates are arranged between the latch circuit and the inputs of the data output buffer. The outputs of the sense amplifier are transmitted to the inputs of the data output buffer through signal paths which bypass the first pass-gates, the latch circuit and the second pass-gates, whereby the data output buffer generates a data output quickly. Thereafter, the first pass-gates and the second pass-gates are controllably brought to a signal-through condition, whereby the output information items of the sense amplifier are stored in the latch circuit. The data output buffer holds the data output in conformity with the stored information items of the latch circuit.

Abstract: A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor.

Abstract: A method for manufacturing a semiconductor substrate comprising the steps of forming on all surfaces of a raw semiconductor substrate an impurity layer of the same conductivity type as the raw semiconductor substrate and forming a first insulating film on the entire impurity layer, removing those portions of the impurity layer and first insulating film which are formed on one major surface of the raw semiconductor substrate and finishing the exposed major surface of the raw semiconductor substrate, thus providing a mirror surface, forming a second insulating film on the mirror surface of the raw semiconductor substrate and on the remaining first insulating film, forming a protective film on the entire second insulating film and forming a third insulating film on the entire protective film, thus providing a laminate, holding the laminate side by side together with other laminates provided in the same way, heating the laminates thus held, in an oxidizing atmosphere, thereby diffusing the impurity from the impur