Abstract: The manufacture of a memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. The manufacture of each load MISFET consists of forming source, drain and channel regions within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film, such as a polycrystalline film, than that of the drive MISFETs. The manufacture of the memory cell having such a stacked arrangement, facilitates the patterning of the source (drain) region and gate electrode of each load MISFET thereof to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes.

Abstract: A memory cell of the type a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETS. Each load MISFET of a memory cell consists of a source, drain and channel region formed within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source (drain) region and gate electrode of each load MISFET thereof are patterned to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes.

Abstract: A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error.

Abstract: A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.

Abstract: In a memory cell of SRAM of CMOS type, load MISFET having a polycrystalline silicon film as area of source, drain and channel is stacked on drive MISFET, and gate electrodes of the drive MISFET and the load MISFET are constituted by conductive films in different layers. Area of source and drain provided on the polycrystalline silicon film has an overlapped area with the gate electrode of the load MISFET.