Patents by Inventor Shigeru Ishii
Shigeru Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120230680Abstract: There is provided a method of determining transmission quality of a path in an optical communication network system obtained by connecting a plurality of networks, the method including: acquiring a value representing transmission performance corresponding to a network condition of each of spans in the path in the optical communication network system; and determining the transmission quality of the path on the basis of the acquired value representing transmission performance corresponding to the network condition of each of spans.Type: ApplicationFiled: February 15, 2012Publication date: September 13, 2012Applicant: FUJITSU LIMITEDInventors: Takehiro Fujita, Shigeru Ishii, Takuya Miyashita
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Publication number: 20120230681Abstract: A storage device stores information regarding a channel from which an optical transmission apparatus at a subsequent stage drops a signal light. A processor determines that switching from second channel transmission using a larger number of channels than a first number of channels to first channel transmission is performed, and controls an attenuation amount, when performing the first channel transmission using the first number of channels, by referring to the storage device according to the determination and making the attenuation amount in a no-signal channel larger than a determine value if the no-signal channel whose wavelength is within a determined range from the wavelength of the signal light channel for the first channel transmission is a channel from which the optical transmission apparatus at the subsequent stage drops a signal light, so as to transmit an amplified spontaneous emission light along the no-signal channel.Type: ApplicationFiled: September 9, 2011Publication date: September 13, 2012Applicant: FUJITSU LIMITEDInventors: Taichi UEKI, Shigeru Ishii
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Publication number: 20120217556Abstract: A semiconductor device featuring a semiconductor chip having a first main surface and a second, opposing main surface and including a MOSFET having source and gate electrodes formed on the first main surface and a drain electrode thereof formed on the second main surface, first and second conductive members acting as lead terminals for the source and gate electrodes, respectively, are disposed over the first main surface, each of the first and second conductive members has a part overlapped with the chip in a plan view, a sealing body sealing the chip and parts of the first and second conductive members such that a part of the first conductive member is projected outwardly from a first side surface of the sealing body and parts of the first and second conductive members are projected outwardly from the opposing second side surface of the sealing body in a plan view.Type: ApplicationFiled: April 30, 2012Publication date: August 30, 2012Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 8183607Abstract: A semiconductor device features a semiconductor chip including a MOSFET, a first electrode of the MOSFET disposed on an obverse surface of the chip, a second, control electrode of the MOSFET disposed on the obverse surface, a third electrode of the MOSFET disposed on a second, opposing surface of the chip, first, second, and third conductive members, each having top surface and opposing bottom surface, the first, second, and third conductive members connecting with the first, second, and third electrodes electrically, respectively, a sealing body having top and bottom surfaces and sealing parts of the first, second, and third conductive members, the first conductive member having first, second, and third contiguous portions, the first portion is positioned over the first electrode, the second is positioned between the first and second portions and the third portion is positioned under the obverse surface of the chip.Type: GrantFiled: July 25, 2011Date of Patent: May 22, 2012Assignees: Renesas Electronics Corporation, Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Publication number: 20110298020Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: ApplicationFiled: July 25, 2011Publication date: December 8, 2011Inventors: Ryoichi KAJIWARA, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Publication number: 20110220451Abstract: In a dry clutch, the space between dry-clutch plates and a bearing, which bearing is interposed between a first piston and a second piston, is blocked off. Also provided is a structure for supplying the bearing with lubricating oil, and thus it is possible to provide the dry clutch, without causing upsizing the bearing.Type: ApplicationFiled: November 25, 2009Publication date: September 15, 2011Inventors: Takashi Kuwahara, Shigeru Ishii
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Publication number: 20110221292Abstract: In a friction coupling device, a restriction mechanism is further provided for restricting relative movement between a cylinder member and a drum member. The restriction mechanism is located on the cylinder-chamber side than friction plates in a pressing direction of a piston, and thus the friction coupling device can realize stable coupling operations without increasing the thickness of an outer wall or the like.Type: ApplicationFiled: November 25, 2009Publication date: September 15, 2011Inventors: Takashi Kuwahara, Shigeru Ishii
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Patent number: 7985991Abstract: A semiconductor device features a semiconductor substrate with a MOSFET, an electrode for main current of the MOSFET disposed on a first major surface of the substrate, an electrode for control of the MOSFET disposed on the first major surface, a rear plane electrode of the MOSFET disposed on a second, opposing surface of the substrate, and an external connection terminal electrically connected to the rear plane electrode, the external electrode contains a first part, a second part and a third part, the first part is positioned over the rear plane electrode, the third part is positioned below the second major surface and the third part is connected via the second part to the first part.Type: GrantFiled: March 12, 2008Date of Patent: July 26, 2011Assignees: Renesas Electronics Corporation, Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 7823410Abstract: In a cooling device for cooling an object to be cooled without using a forced cold air circulating system, which circulates cold air forcibly, a cooling device at a practical level is provided, and a cooling device capable of achieving a sufficient cooling effect is provided. A cooler 18 is provided in an interior that is insulated adiabatically from an exterior, a cooling fan 20 is disposed on a front surface of the cooler 18, a cooling chamber 22 in which an object to be cooled is placed is defined by a space in front of the cooling fan 20, a cooled air behind the cooling fan 20 is drawn with the fan and allowed to flow into the cooling chamber 22, and a/D=½ to ¼ is satisfied, where a indicates a dimension of a gap between the cooler 18 and the cooling fan 20 along a front-back direction and D indicates a diameter of the cooling fan 20.Type: GrantFiled: October 26, 2004Date of Patent: November 2, 2010Assignee: Air Operation Technologies Inc.Inventors: Shigeru Ishii, Kazunori Terasaki
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Publication number: 20100160111Abstract: A belt continuously-variable transmission control apparatus includes: a belt continuously-variable transmission including; a primary pulley arranged to receive a torque from a driving source; a secondary pulley arranged to output the torque to driving wheels; a belt wound around the primary pulley and the secondary pulley; a hydraulic pressure control section configured to control a hydraulic pressure of one of the primary pulley and the secondary pulley which is a capacity side, and thereby to bring the belt, the primary pulley and the secondary pulley to a slip state; and a torque control section configured to control the torque of the driving source, and thereby to bring the slip state to a predetermined slip state.Type: ApplicationFiled: December 17, 2009Publication date: June 24, 2010Inventors: Tsuyoshi YAMANAKA, Shigeru Ishii, Shigeki Shimanaka
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Publication number: 20100111536Abstract: A communication network includes a starting node that has a variable dispersion compensator that performs dispersion compensation at a variable dispersion compensation amount such that a residual dispersion amount of an optical signal transmitted therethrough becomes a predetermined reference residual dispersion amount; and plural nodes that are subjected to dispersion compensation design using the starting node as a starting point and that include fixed dispersion compensators selected based on the reference residual dispersion amount.Type: ApplicationFiled: December 9, 2009Publication date: May 6, 2010Applicant: Fujitsu LimitedInventors: Shigeru Ishii, Takehiro Fujita
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Patent number: 7692564Abstract: The invention eliminates a race condition without restricting reception speed. The invention provides a method of designing a serial-to-parallel conversion circuit, the method including determining a rule for data and a strobe when a first-stage memory device in a shift register latches data and when the memory device holds the data; providing a logical circuit for generating an output conforming to the rule at a data input side of the shift register; and shifting a data latch timing of the memory device by a half-period.Type: GrantFiled: July 10, 2008Date of Patent: April 6, 2010Assignee: Mitsubishi Heavy Industries, Ltd.Inventors: Shigeru Ishii, Masaharu Nomachi
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Patent number: 7644747Abstract: A rectangular substrate dividing apparatus, which can divide a rectangular substrate in a smaller space, accommodate devices, formed as individual pieces by the division, into device cases, and pick up the devices reliably and efficiently from a protective tape affixed to the back of the rectangular substrate, is provided. This apparatus separates a rectangular substrate, to whose back a protective tape is affixed and on which a plurality of devices are partitioned by a lattice of scheduled-separation lines, along the scheduled-separation lines to divide the rectangular substrate into the individual devices, and accommodates the devices in device cases. In a cutting-responsible region, the rectangular substrate is carried out of cassettes, cut by a cutter, and then cleaned by a cleaner. In a tape peeling-responsible region, the devices are picked up with the protective tape being peeled off. In a device accommodation-responsible region, the picked-up individual devices are accommodated into device cases.Type: GrantFiled: November 29, 2005Date of Patent: January 12, 2010Assignee: Disco CorporationInventors: Satoshi Ohkawara, Kuniharu Izumi, Shigeru Ishii, Ryu Komine
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Publication number: 20090015449Abstract: The invention eliminates a race condition without restricting reception speed. The invention provides a method of designing a serial-to-parallel conversion circuit, the method including determining a rule for data and a strobe when a first-stage memory device in a shift register latches data and when the memory device holds the data; providing a logical circuit for generating an output conforming to the rule at a data input side of the shift register; and shifting a data latch timing of the memory device by a half-period.Type: ApplicationFiled: July 10, 2008Publication date: January 15, 2009Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Shigeru Ishii, Masaharu Nomachi
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Publication number: 20080169537Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: ApplicationFiled: March 12, 2008Publication date: July 17, 2008Inventors: Ryoichi KAJIWARA, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 7400002Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: GrantFiled: October 31, 2006Date of Patent: July 15, 2008Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 7394146Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: GrantFiled: October 31, 2006Date of Patent: July 1, 2008Assignees: Renesas Tehcnology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 7342267Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: GrantFiled: May 2, 2006Date of Patent: March 11, 2008Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 7332757Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: GrantFiled: May 2, 2006Date of Patent: February 19, 2008Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Publication number: 20070074530Abstract: In a cooling device for cooling an object to be cooled without using a forced cold air circulating system, which circulates cold air forcibly, a cooling device at a practical level is provided, and a cooling device capable of achieving a sufficient cooling effect is provided. A cooler 18 is provided in an interior that is insulated adiabatically from an exterior, a cooling fan 20 is disposed on a front surface of the cooler 18, a cooling chamber 22 in which an object to be cooled is placed is defined by a space in front of the cooling fan 20, a cooled air behind the cooling fan 20 is drawn with the fan and allowed to flow into the cooling chamber 22, and a/D=½ to ¼ is satisfied, where a indicates a dimension of a gap between the cooler 18 and the cooling fan 20 along a front-back direction and D indicates a diameter of the cooling fan 20.Type: ApplicationFiled: October 26, 2004Publication date: April 5, 2007Inventor: Shigeru Ishii