Patents by Inventor Shigeru Mizuno
Shigeru Mizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7935393Abstract: Embodiments of a method and system for improving the consistency of a layer or a plurality of layers with a desired profile in a deposition system are generally described herein. Other embodiments may be described and claimed.Type: GrantFiled: August 7, 2007Date of Patent: May 3, 2011Assignee: Tokyo Electron LimitedInventors: Shigeru Mizuno, Takashi Sakuma, Yasushi Mizusawa
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Publication number: 20110076390Abstract: Methods are provided for multi-step Cu metal plating on a continuous Ru metal film in recessed features found in advanced integrated circuits. The use of a continuous Ru metal film prevents formation of undesirable micro-voids during Cu metal filling of high-aspect-ratio recessed features, such as trenches and vias, and enables formation of large Cu metal grains that include a continuous Cu metal layer plated onto the continuous Ru metal film. The large Cu grains lower the electrical resistivity of the Cu filled recessed features and increase the reliability of the integrated circuit.Type: ApplicationFiled: September 30, 2009Publication date: March 31, 2011Applicants: TOKYO ELECTRON LIMITED, NOVELLUS SYSTEMS, INC.Inventors: Frank M. Cerio, JR., Shigeru Mizuno, Jonathan Reid, Thomas Ponnuswamy
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Patent number: 7846841Abstract: A method is provided for integrating cobalt nitride cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt nitride cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k dielectric regions, and selectively forming a cobalt nitride cap layer on the Cu paths relative to the low-k dielectric regions.Type: GrantFiled: September 30, 2008Date of Patent: December 7, 2010Assignee: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Shigeru Mizuno, Miho Jomen
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Patent number: 7848077Abstract: An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.Type: GrantFiled: October 28, 2009Date of Patent: December 7, 2010Assignee: Canon Anelva CorporationInventors: Shigeru Mizuno, Masahito Ishihara, Sunil Wickramanayaka, Naoki Miyazaki
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Patent number: 7807561Abstract: After plural semiconductor elements are stacked to form a stacked body P, side wirings are formed on the side surface of the stacked body P, thereby manufacturing a semiconductor apparatus in which the respective semiconductor elements are electrically connected to one another. In this case, as the semiconductor element, a semiconductor element 10 is employed in which a gold wire 16 with its one end connected to an electrode terminal of the semiconductor element is extended out to the side surface. A conductive paste 36 containing conductive particles applied over a predetermined length of a transferring wire 30 is transferred to the side surface of the stacked body P so that the gold wires 16 extended out to the side surfaces of the semiconductor elements 10, 10, 10 are connected, thereby forming the side wirings.Type: GrantFiled: July 18, 2008Date of Patent: October 5, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventors: Shigeru Mizuno, Takashi Kurihara, Akinori Shiraishi, Kei Murayama, Mitsutoshi Higashi
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Publication number: 20100248473Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.Type: ApplicationFiled: March 31, 2009Publication date: September 30, 2010Applicant: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Shigeru Mizuno, Satohiko Hoshino, Hiroyuki Nagai, Yuki Chiba, Frank M. Cerio, JR.
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Patent number: 7799681Abstract: A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface and a dielectric layer surface, depositing first Ru metal on the Cu metal surface, and depositing additional Ru metal on the dielectric layer surface, where the amount of the additional Ru metal is less than the amount of the first Ru metal. The method further includes at least substantially removing the additional Ru metal from the dielectric layer surface to improve the selective formation of a Ru metal cap layer on the Cu metal surface. Other embodiments further include incorporating one or more types of modifier elements into the dielectric layer surface, the Cu metal surface, the Ru metal cap layer, or a combination thereof.Type: GrantFiled: July 15, 2008Date of Patent: September 21, 2010Assignee: Tokyo Electron LimitedInventors: Kenji Suzuki, Frank M. Cerio, Jr., Miho Jomen, Shigeru Mizuno, Yasushi Mizusawa, Tadahiro Ishizaka
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Patent number: 7791857Abstract: An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.Type: GrantFiled: December 30, 2008Date of Patent: September 7, 2010Assignee: Canon Anelva CorporationInventors: Shigeru Mizuno, Masahito Ishihara, Sunil Wickramanayaka, Naoki Miyazaki
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Publication number: 20100210108Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. In one embodiment, the method includes providing a patterned substrate containing Cu metal surfaces and dielectric layer surfaces, exposing the patterned substrate to a process gas comprising a metal-containing precursor, and irradiating the patterned substrate with electromagnetic radiation, where selective metal-containing cap layer formation on the Cu metal surfaces is facilitated by the electromagnetic radiation. In some embodiments, the method further includes pre-treating the patterned substrate with additional electromagnetic radiation and optionally a cleaning gas prior to forming the metal-containing cap layer.Type: ApplicationFiled: February 13, 2009Publication date: August 19, 2010Applicant: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Shigeru Mizuno
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Patent number: 7777349Abstract: A plurality of quadrilateral-shaped semiconductor elements are stacked on the one surface of a circuit substrate. A side surface wiring for making electrical connection between each of the electrode terminals of the semiconductor elements and a pad formed on the circuit substrate is formed by applying a conductive paste containing conductive particles. A metal wire whose one end is connected to the electrode terminal is extended along a tapered surface formed by cutting off an edge of the electrode terminal surface on which the electrode terminal is formed among edges formed along each of the sides of the semiconductor element. At least a part of the metal wire extended from each of the electrode terminals of the semiconductor elements to the tapered surface is electrically connected to the side surface wiring.Type: GrantFiled: July 18, 2008Date of Patent: August 17, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kei Murayama, Shigeru Mizuno, Takashi Kurihara, Akinori Shiraishi, Mitsutoshi Higashi
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Patent number: 7750484Abstract: A method of manufacturing a semiconductor device in which a semiconductor element 10 is mounted on a substrate 20 through a flip-chip connection, includes the steps of cladding gallium as a bonding material 30 to a connecting pad 22 formed on a surface of the substrate 20, diffusing copper from the connecting pad 22 formed of the copper into the bonding material 30 through heating under vacuum, thereby bringing a state of a solid solution of the gallium and the copper, and aligning a connecting bump 12 formed on the semiconductor element 10 with the connecting pad 22 and bonding the connecting bump 12 to the connecting pad 22 through the bonding material 30 in a state of a solid solution under heating.Type: GrantFiled: June 25, 2008Date of Patent: July 6, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventors: Shigeru Mizuno, Takashi Kurihara
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Patent number: 7731187Abstract: A sheet medium adjustment apparatus, e.g., in an image forming system, includes: an ejector to eject a conveyed sheet; a stacking device to stack each sheet ejected from the sheet ejector into a stack on a tray; a moving device to shift the stacking device in a movement direction perpendicular to a sheet-ejecting direction; a sheet aligning member to align ends of the sheets in the stack that are parallel to the sheet-ejecting direction; a stepping motor to move the sheet aligning member; and an evacuation device to evacuate the aligning member by an amount representing an evacuation displacement in the movement direction at a timing of aligning the sheet, the evacuation displacement being determined adaptively according to at least one of an attribute of a given sheet in the stack, an attribute of the stack as a whole and an attribute of the tray.Type: GrantFiled: January 30, 2007Date of Patent: June 8, 2010Assignee: Ricoh Co., Ltd.Inventors: Toru Horio, Minoru Hattori, Shigeru Mizuno, Ikumi Takashima, Koji Furuta, Masanobu Kimata, Miyuki Ito, Yoshihide Sugiyama, Akihiro Tsuno, Nakayama Naoya, Ueno Shinichi
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Patent number: 7727883Abstract: A method of forming an interconnect structure is provided. The method includes depositing a cobalt metal layer in an interconnect opening formed within a dielectric material containing a dielectric reactant element. The method further includes, in any order, thermally reacting at least a portion of the cobalt metal layer with at least a portion of the dielectric material to form a diffusion barrier containing a compound of the reactive metal from the cobalt metal layer and the dielectric reactant element from the dielectric material, and forming a cobalt nitride adhesion layer in the interconnect opening. The method further includes filling the interconnect opening with Cu metal, where the diffusion barrier and the cobalt nitride adhesion layer surround the Cu metal in the interconnect opening.Type: GrantFiled: September 30, 2008Date of Patent: June 1, 2010Assignee: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Shigeru Mizuno
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Patent number: 7724493Abstract: An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.Type: GrantFiled: October 22, 2008Date of Patent: May 25, 2010Assignee: Canon Anelva CorporationInventors: Shigeru Mizuno, Masahito Ishihara, Sunil Wickramanayaka, Naoki Miyazaki
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Patent number: 7718527Abstract: A method is provided for integrating cobalt tungsten cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt tungsten cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k regions, and forming a cobalt tungsten cap layer on the Cu paths.Type: GrantFiled: October 1, 2008Date of Patent: May 18, 2010Assignee: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Shigeru Mizuno, Miho Jomen
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Publication number: 20100081274Abstract: A method is provided for integrating ruthenium (Ru) metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. Embodiments of the invention include treating patterned substrates containing metal layers and low-k dielectric materials with NHx (x?3) radicals and H radicals to improve selective formation of ruthenium (Ru) metal cap layers on the metal layers relative to the low-k dielectric materials.Type: ApplicationFiled: September 29, 2008Publication date: April 1, 2010Applicant: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Shigeru Mizuno, Frank M. Cerio, JR.
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Publication number: 20100081275Abstract: A method is provided for integrating cobalt nitride cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt nitride cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k dielectric regions, and selectively forming a cobalt nitride cap layer on the Cu paths relative to the low-k dielectric regions.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Applicant: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Shigeru Mizuno, Miho Jomen
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Publication number: 20100081271Abstract: A method of forming an interconnect structure is provided. The method includes depositing a cobalt metal layer in an interconnect opening formed within a dielectric material containing a dielectric reactant element. The method further includes, in any order, thermally reacting at least a portion of the cobalt metal layer with at least a portion of the dielectric material to form a diffusion barrier containing a compound of the reactive metal from the cobalt metal layer and the dielectric reactant element from the dielectric material, and forming a cobalt nitride adhesion layer in the interconnect opening. The method further includes filling the interconnect opening with Cu metal, where the diffusion barrier and the cobalt nitride adhesion layer surround the Cu metal in the interconnect opening.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Applicant: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Shigeru Mizuno
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Publication number: 20100078818Abstract: An interconnect structure is provided. The interconnect structure includes an interconnect opening formed within a dielectric material, a diffusion barrier on the dielectric material, where the diffusion barrier contains a compound from a thermal reaction between cobalt (Co) metal from at least a portion of a cobalt metal layer formed on the dielectric material and a dielectric reactant element from the dielectric material. The interconnect structure further includes a cobalt nitride adhesion layer in the interconnect opening, and a Cu metal fill in the interconnect opening, wherein the diffusion barrier and the cobalt nitride adhesion layer surround the Cu metal fill within the interconnect opening.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Applicant: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Shigeru Mizuno
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Publication number: 20100081276Abstract: A method is provided for integrating cobalt tungsten cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt tungsten cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k regions, and forming a cobalt tungsten cap layer on the Cu paths.Type: ApplicationFiled: October 1, 2008Publication date: April 1, 2010Applicant: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Shigeru Mizuno, Miho Jomen