Patents by Inventor Shih-Chang Liu

Shih-Chang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220131072
    Abstract: A memory device includes a bottom electrode, a magnetic tunnel junction (MTJ) structure, an inner spacer, and an outer spacer. The MTJ structure is over the bottom electrode. The bottom electrode has a top surface extending past opposite sidewalls of the MTJ structure. The inner spacer contacts the top surface of the bottom electrode and one of the opposite sidewalls of the MTJ structure. The outer spacer contacts an outer sidewall of the inner spacer. The outer spacer protrudes from a top surface of the inner spacer by a step height.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Ting SUNG, Chern-Yow HSU, Shih-Chang LIU
  • Patent number: 11296100
    Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Chyi Liu, Shih-Chang Liu, Sheng-Chieh Chen, Yu-Hsing Chang
  • Publication number: 20220102155
    Abstract: In some methods, a first recess is etched in a selected region of a substrate. A first polymer liner is formed on sidewalls and a bottom surface of the first recess. A portion of the first polymer liner is removed from the bottom surface, and a remaining portion of the first polymer liner is left along the sidewalls. The first recess is deepened to establish a second recess while the remaining portion of the first polymer liner is left along the sidewalls. A first oxide liner is formed along the sidewalls and along sidewalls and a bottom surface of the second recess. A portion of the first oxide liner is removed from a bottom surface of the second recess, while a remaining portion of the first oxide liner is left on the sidewalls of the first recess and the sidewalls of the second recess.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Yu-Hsing Chang, Ming Chyi Liu, Shih-Chang Liu
  • Patent number: 11289539
    Abstract: Pillar stacks of a top electrode and a hard mask portion are formed over a layer stack containing a continuous reference magnetization layer, a continuous nonmagnetic tunnel barrier layer, and a continuous free magnetization layer. A continuous dielectric liner may be deposited and anisotropically etched to form inner dielectric spacers. The continuous free magnetization layer, the continuous nonmagnetic tunnel barrier layer, and the continuous reference magnetization layer may be anisotropically etched to form vertical stacks of a respective reference magnetization layer, a respective nonmagnetic tunnel barrier layer, and a respective free magnetization layer, which are magnetic tunnel junctions. The inner dielectric spacers prevent redeposition of a metallic material of the hard mask portions on sidewalls of the magnetic tunnel junctions. The hard mask portions may be removed, and a metallic cell contact structures may be formed on top of each top electrode.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Min-Yung Ko, Shih-Chang Liu
  • Patent number: 11289648
    Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 11289651
    Abstract: A memory cell with a hard mask and a sidewall spacer of different material is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A hard mask disposed over the top electrode. A sidewall spacer extends upwardly along sidewalls of the switching dielectric, the top electrode, and the hard mask. The hard mask and the sidewall spacer have different etch selectivity. A method for manufacturing the memory cell is also provided.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Hsueh Yang, Shih-Chang Liu, Yuan-Tai Tseng
  • Publication number: 20220069204
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.
    Type: Application
    Filed: October 23, 2020
    Publication date: March 3, 2022
    Inventors: Min-Yung Ko, Chern-Yow Hsu, Chang-Ming Wu, Shih-Chang Liu
  • Patent number: 11258007
    Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Publication number: 20220028985
    Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.
    Type: Application
    Filed: October 12, 2021
    Publication date: January 27, 2022
    Inventors: SHENG-CHIEH CHEN, MING CHYI LIU, SHIH-CHANG LIU
  • Patent number: 11233145
    Abstract: Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: January 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Sheng-De Liu, Chung-Yen Chou, Shih-Chang Liu
  • Patent number: 11227993
    Abstract: A device includes a first conductive via plug, a first electrode, a storage element, a second electrode, a spacer, a barrier structure, a first dielectric layer. The first electrode is over the first conductive via plug. The storage element is over the first electrode. The second electrode is over the storage element. The spacer has a bottom portion extending along a top surface of the first electrode and a standing portion extending from the bottom portion and along a sidewall of the second electrode. The barrier structure extends from the bottom portion of the spacer and along a sidewall of the standing portion of the spacer. The first dielectric layer is substantially conformally over the spacer and the barrier structure.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 11222896
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Ming Chyi Liu, Shih-Chang Liu, Xiaomeng Chen
  • Patent number: 11217596
    Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chieh Chen, Ming Chyi Liu, Shih-Chang Liu
  • Publication number: 20210375988
    Abstract: Pillar stacks of a top electrode and a hard mask portion are formed over a layer stack containing a continuous reference magnetization layer, a continuous nonmagnetic tunnel barrier layer, and a continuous free magnetization layer. A continuous dielectric liner may be deposited and anisotropically etched to form inner dielectric spacers. The continuous free magnetization layer, the continuous nonmagnetic tunnel barrier layer, and the continuous reference magnetization layer may be anisotropically etched to form vertical stacks of a respective reference magnetization layer, a respective nonmagnetic tunnel barrier layer, and a respective free magnetization layer, which are magnetic tunnel junctions. The inner dielectric spacers prevent redeposition of a metallic material of the hard mask portions on sidewalls of the magnetic tunnel junctions. The hard mask portions may be removed, and a metallic cell contact structures may be formed on top of each top electrode.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Inventors: Min-Yung KO, Shih-Chang LIU
  • Patent number: 11189789
    Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 11189787
    Abstract: A phase change memory (PCM) cell with a low deviation contact area between a heater and a phase change element is provided. The PCM cell comprises a bottom electrode, a dielectric layer, a heater, a phase change element, and a top electrode. The dielectric layer overlies the bottom electrode. The heater extends upward from the bottom electrode, through the dielectric layer. Further, the heater has a top surface that is substantially planar and that is spaced below a top surface of the dielectric layer. The phase change element overlies the dielectric layer and protrudes into the dielectric layer to contact with the top surface of the heater. Also provided is a method for manufacturing the PCM cell.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Jen Tsai, Shih-Chang Liu
  • Publication number: 20210367145
    Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 25, 2021
    Inventors: CHUNG-YEN CHOU, FU-TING SUNG, YAO-WEN CHANG, SHIH-CHANG LIU
  • Publication number: 20210359003
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect disposed within a dielectric structure over a substrate. A memory device includes a data storage structure disposed between a bottom electrode and a top electrode. The bottom electrode is electrically coupled to the lower interconnect. A sidewall spacer includes an interior sidewall that continuously extends from along an outermost sidewall of the top electrode to below an outermost sidewall of the bottom electrode. The sidewall spacer further includes an outermost sidewall that extends from a bottom surface of the sidewall spacer to above a top of the bottom electrode.
    Type: Application
    Filed: July 30, 2021
    Publication date: November 18, 2021
    Inventors: Yuan-Tai Tseng, Chung-Chiang Min, Shih-Chang Liu
  • Publication number: 20210351348
    Abstract: A memory cell with hard mask insulator and its manufacturing methods are provided. In some embodiments, a memory cell stack is formed over a substrate having a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is formed over the top electrode layer. A first metal hard masking layer is formed over the first insulating layer. Then, a series of etch is performed to pattern the first metal hard masking layer, the first insulating layer, the top electrode layer and the resistance switching dielectric layer to form a first metal hard mask, a hard mask insulator, a top electrode, and a resistance switching dielectric.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 11, 2021
    Inventors: Chern-Yow Hsu, Chung-Chiang Min, Shih-Chang Liu
  • Patent number: 11171147
    Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chieh Chen, Ming Chyi Liu, Shih-Chang Liu