Patents by Inventor Shih-Chang Liu

Shih-Chang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11374000
    Abstract: Various embodiments of the present application are directed towards a semiconductor device comprising a trench capacitor, the trench capacitor comprising a plurality of lateral protrusions. In some embodiments, the trench capacitor comprises a dielectric structure over a substrate. The dielectric structure may comprise a plurality of dielectric layers overlying the substrate. The dielectric structure may comprise a plurality of lateral recesses. In some embodiments, the plurality of lateral protrusions extend toward and fill the plurality of lateral recesses. By forming the trench capacitor with the plurality of lateral protrusions filling the plurality of lateral recesses, the surface area of the capacitor is increased without increasing the depth of the trench. As a result, greater capacitance values may be achieved without necessarily increasing the depth of the trench and thus, without necessarily increasing the size of the semiconductor device.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Liang Lee, Ming Chyi Liu, Shih-Chang Liu
  • Publication number: 20220199759
    Abstract: A deep trench is formed in a substrate, and a layer stack including at least three metallic electrode plates interlaced with at least two node dielectric layers is formed in, and over, the deep trench. A contact-level dielectric material layer over the layer stack, and contact via cavities are formed therethrough. The depths of the contact via cavities are differentiated by selectively increasing the depth of a respective subset of the contact via cavities by performing at least twice a combination of processing steps that includes an etch mask formation process and an etch process. A combination of a dielectric contact via liner and a plate contact via structure can be formed within each of the contact via cavities. Plate contact via structures that extend through any metallic electrode plate can be electrically isolated from such a metallic electrode plate by a respective dielectric contact via liner.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Inventors: Ming CHYI LIU, Yu-Hsing CHANG, Shih-Chang LIU
  • Patent number: 11367832
    Abstract: A method of making a magnetoresistive random access memory (MRAM) device includes forming a bottom conductive layer. The method includes forming an anti-ferromagnetic layer over the bottom conductive layer and forming a tunnel layer over the anti-ferromagnetic layer. The method includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer, wherein the anti-ferromagnetic layer, the tunnel layer and the free magnetic layer are part of a magnetic tunnel junction (MTJ) unit. The method includes forming a top conductive layer over the free magnetic layer. The method includes performing at least one lithographic process to remove portions of the bottom conductive layer, the MTJ unit and the top conductive layer that is uncovered by a photoresist layer. The method includes removing a portion of a sidewall of the MTJ unit.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Publication number: 20220190240
    Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 16, 2022
    Inventors: Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 11361971
    Abstract: In some methods, a first recess is etched in a selected region of a substrate. A first polymer liner is formed on sidewalls and a bottom surface of the first recess. A portion of the first polymer liner is removed from the bottom surface, and a remaining portion of the first polymer liner is left along the sidewalls. The first recess is deepened to establish a second recess while the remaining portion of the first polymer liner is left along the sidewalls. A first oxide liner is formed along the sidewalls and along sidewalls and a bottom surface of the second recess. A portion of the first oxide liner is removed from a bottom surface of the second recess, while a remaining portion of the first oxide liner is left on the sidewalls of the first recess and the sidewalls of the second recess.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsing Chang, Ming Chyi Liu, Shih-Chang Liu
  • Patent number: 11362265
    Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Fu-Ting Sung, Chung-Chiang Min, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 11348935
    Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai
  • Publication number: 20220131072
    Abstract: A memory device includes a bottom electrode, a magnetic tunnel junction (MTJ) structure, an inner spacer, and an outer spacer. The MTJ structure is over the bottom electrode. The bottom electrode has a top surface extending past opposite sidewalls of the MTJ structure. The inner spacer contacts the top surface of the bottom electrode and one of the opposite sidewalls of the MTJ structure. The outer spacer contacts an outer sidewall of the inner spacer. The outer spacer protrudes from a top surface of the inner spacer by a step height.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Ting SUNG, Chern-Yow HSU, Shih-Chang LIU
  • Patent number: 11296100
    Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Chyi Liu, Shih-Chang Liu, Sheng-Chieh Chen, Yu-Hsing Chang
  • Publication number: 20220102155
    Abstract: In some methods, a first recess is etched in a selected region of a substrate. A first polymer liner is formed on sidewalls and a bottom surface of the first recess. A portion of the first polymer liner is removed from the bottom surface, and a remaining portion of the first polymer liner is left along the sidewalls. The first recess is deepened to establish a second recess while the remaining portion of the first polymer liner is left along the sidewalls. A first oxide liner is formed along the sidewalls and along sidewalls and a bottom surface of the second recess. A portion of the first oxide liner is removed from a bottom surface of the second recess, while a remaining portion of the first oxide liner is left on the sidewalls of the first recess and the sidewalls of the second recess.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Yu-Hsing Chang, Ming Chyi Liu, Shih-Chang Liu
  • Patent number: 11289651
    Abstract: A memory cell with a hard mask and a sidewall spacer of different material is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A hard mask disposed over the top electrode. A sidewall spacer extends upwardly along sidewalls of the switching dielectric, the top electrode, and the hard mask. The hard mask and the sidewall spacer have different etch selectivity. A method for manufacturing the memory cell is also provided.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Hsueh Yang, Shih-Chang Liu, Yuan-Tai Tseng
  • Patent number: 11289539
    Abstract: Pillar stacks of a top electrode and a hard mask portion are formed over a layer stack containing a continuous reference magnetization layer, a continuous nonmagnetic tunnel barrier layer, and a continuous free magnetization layer. A continuous dielectric liner may be deposited and anisotropically etched to form inner dielectric spacers. The continuous free magnetization layer, the continuous nonmagnetic tunnel barrier layer, and the continuous reference magnetization layer may be anisotropically etched to form vertical stacks of a respective reference magnetization layer, a respective nonmagnetic tunnel barrier layer, and a respective free magnetization layer, which are magnetic tunnel junctions. The inner dielectric spacers prevent redeposition of a metallic material of the hard mask portions on sidewalls of the magnetic tunnel junctions. The hard mask portions may be removed, and a metallic cell contact structures may be formed on top of each top electrode.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Min-Yung Ko, Shih-Chang Liu
  • Patent number: 11289648
    Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Tai Tseng, Shih-Chang Liu
  • Publication number: 20220069204
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.
    Type: Application
    Filed: October 23, 2020
    Publication date: March 3, 2022
    Inventors: Min-Yung Ko, Chern-Yow Hsu, Chang-Ming Wu, Shih-Chang Liu
  • Patent number: 11258007
    Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Publication number: 20220028985
    Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.
    Type: Application
    Filed: October 12, 2021
    Publication date: January 27, 2022
    Inventors: SHENG-CHIEH CHEN, MING CHYI LIU, SHIH-CHANG LIU
  • Patent number: 11233145
    Abstract: Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: January 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Sheng-De Liu, Chung-Yen Chou, Shih-Chang Liu
  • Patent number: 11227993
    Abstract: A device includes a first conductive via plug, a first electrode, a storage element, a second electrode, a spacer, a barrier structure, a first dielectric layer. The first electrode is over the first conductive via plug. The storage element is over the first electrode. The second electrode is over the storage element. The spacer has a bottom portion extending along a top surface of the first electrode and a standing portion extending from the bottom portion and along a sidewall of the second electrode. The barrier structure extends from the bottom portion of the spacer and along a sidewall of the standing portion of the spacer. The first dielectric layer is substantially conformally over the spacer and the barrier structure.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 11222896
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Ming Chyi Liu, Shih-Chang Liu, Xiaomeng Chen
  • Patent number: 11217596
    Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chieh Chen, Ming Chyi Liu, Shih-Chang Liu