Patents by Inventor Shih-Fu Huang

Shih-Fu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10441834
    Abstract: This invention discloses an exercise machine with adjustable resistance. The exercise machine includes a fluid container, one or more paddles, a driving device, and an adjusting device. The one or more paddles are arranged in the fluid container into which a fluid is poured. The driving device comprises an adjusting rod to couple with the one or more paddles. The driving device transmits a user's force for driving the one or more paddles to rotate. The adjusting device can adjust a depth of the one or more paddles in the fluid, so as to provide differing degrees of resistance for the one or more paddles.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: October 15, 2019
    Assignee: Dyaco International Inc.
    Inventors: Shih-Wei Liu, Hsuan-Fu Huang
  • Patent number: 10434707
    Abstract: A touch substrate manufactured by three-dimensional printing and a method for manufacturing the same are disclosed. The method for manufacturing the touch substrate works together with a three-dimensional printer. The three-dimensional printer includes a first nozzle, a second nozzle, and a light source. The method includes the steps of: jetting a photocuring material by the first nozzle and exposing the photocuring material to the light source to form a base layer; jetting a conductive material on the base layer by the second nozzle and exposing the conductive material to the light source to form a touch electrode layer; and jetting the photocuring material on the base layer and the touch electrode layer by the first nozzle and exposing the photocuring material to the light source to form a protective layer. The touch electrode layer is embedded between the base layer and the protective layer.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 8, 2019
    Assignee: TPK Universal Solutions Limited
    Inventors: Shun-Jie Yang, Shun-Ta Chien, Shih-Ching Chen, Wen-Fu Huang
  • Publication number: 20190229233
    Abstract: A light-emitting device is provided. The light-emitting device comprises a substrate; an insulating layer on the substrate, wherein the insulating layer comprises a first hole; a light-emitting stack on the insulating layer and comprising an active region comprising a top surface, wherein the top surface comprises a first part and a second part; and an opaque layer covering the first part of the top surface and exposing the second part of the top surface, wherein the second part is directly above the first hole.
    Type: Application
    Filed: April 3, 2019
    Publication date: July 25, 2019
    Inventors: Cheng-Feng YU, Ching-Yuan TSAI, Yao-Ru CHANG, Hsin-Chan CHUNG, Shih-Chang LEE, Wen-Luh LIAO, Cheng-Hsing CHIANG, Kuo-Feng HUANG, Hsu-Hsuan TENG, Hung-Ta CHENG, Yung-Fu CHANG
  • Publication number: 20190219252
    Abstract: The present invention relates to a light emitting device comprising a transparent substrate which light can pass through and at least one LED chip emitting light omni-directionally. Wherein the LED chip is disposed on one surface of the substrate and the light emitting angle of the LED chip is wider than 180°, and the light emitted by the LED chip will penetrate into the substrate and at least partially emerge from another surface of the substrate. According to the present invention, the light emitting device using LED chips can provide sufficient lighting intensity and uniform lighting performance.
    Type: Application
    Filed: March 26, 2019
    Publication date: July 18, 2019
    Inventors: CHI-CHIH PU, CHEN-HONG LEE, SHIH-YU YEH, WEI-KANG CHENG, SHYI-MING PAN, SIANG-FU HONG, CHIH-SHU HUANG, TZU-HSIANG WANG, SHIH-CHIEH TANG, CHENG-KUANG YANG
  • Patent number: 10325634
    Abstract: The present invention provides a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory is disclosed. The exemplary differential sensing circuit comprises: a dynamic voltage reference generating unit and a differential sensing amplifying unit. The dynamic voltage reference generating unit is coupled to an input voltage, and utilized for receiving a setting signal to generate the dynamic voltage reference. The differential sensing amplifying unit is coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, and utilized for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: June 18, 2019
    Assignee: MediaTek Inc.
    Inventors: Shih-Huang Huang, Rei-Fu Huang
  • Patent number: 10312407
    Abstract: A light-emitting device is provided. The light-emitting device comprises a substrate; an insulating layer on the substrate, wherein the insulating layer comprises a first hole; a light-emitting stack on the insulating layer and comprising an active region comprising a top surface, wherein the top surface comprises a first part and a second part; and an opaque layer covering the first part of the top surface and exposing the second part of the top surface, wherein the second part is directly above the first hole.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: June 4, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Cheng-Feng Yu, Ching-Yuan Tsai, Yao-Ru Chang, Hsin-Chan Chung, Shih-Chang Lee, Wen-Luh Liao, Cheng-Hsing Chiang, Kuo-Feng Huang, Hsu-Hsuan Teng, Hung-Ta Cheng, Yung-Fu Chang
  • Patent number: 10288258
    Abstract: The lighting module includes a light emitter, a hood and a cover. The light emitter is mounted on an end of the hood. The cover is disposed in the hood and has a conic reflecting surface. When the light emitter is lit up, the lights are emitted into the hood and reflected by the conic reflecting surface and then further reflected by the hood to be projected outward.
    Type: Grant
    Filed: December 31, 2017
    Date of Patent: May 14, 2019
    Inventors: Shih-Fu Huang, Wei-Jung Lee
  • Patent number: 9564346
    Abstract: A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 7, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen
  • Patent number: 9548138
    Abstract: A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: January 17, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ying-Tsai Ting, Che-Chin Wu, Tsung-Yi Chou, Shih-Fu Huang
  • Patent number: 9406658
    Abstract: An embedded component device includes an electronic component including an electrical contact, an upper patterned conductive layer, a dielectric layer between the upper patterned conductive layer and the electronic component, a first electrical interconnect, a lower patterned conductive layer, a conductive via, and a second electrical interconnect. The dielectric layer has a first opening exposing the electrical contact, and a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer. The first electrical interconnect extends from the electrical contact to the upper patterned conductive layer, and fills the first opening. The second opening has an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer. The conductive via is located at the lower portion of the second opening. The second electrical interconnect fills the upper portion of the second opening.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: August 2, 2016
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Che Lee, Yuan-Chang Su, Ming Chiang Lee, Shih-Fu Huang
  • Publication number: 20160218019
    Abstract: A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 28, 2016
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Chang SU, Shih-Fu HUANG, Chia-Cheng CHEN
  • Patent number: 9305638
    Abstract: Operation methods for a memory device is provided. An operation method for the memory device comprises programming the memory device as described in follows. Data are provided. The data comprise a plurality of codes. Each number of the codes is counted. Then, a mapping rule is generated according to each number of the codes. In the mapping rule, each of the codes is mapped to one of a plurality of verifying voltage levels which are sequentially arranged from low to high. After that, the data are programmed into the memory device according to the mapping rule.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: April 5, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Ming Chang, Yung-Chun Li, Chih-Chang Hsieh, Shih-Fu Huang, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
  • Publication number: 20160064103
    Abstract: A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once.
    Type: Application
    Filed: September 2, 2014
    Publication date: March 3, 2016
    Inventors: Ying-Tsai Ting, Che-Chin Wu, Tsung-Yi Chou, Shih-Fu Huang
  • Patent number: 9196597
    Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: November 24, 2015
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt
  • Patent number: 9165900
    Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) a patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: October 20, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Chia-Hsiung Hsieh, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh
  • Publication number: 20140346670
    Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.
    Type: Application
    Filed: August 6, 2014
    Publication date: November 27, 2014
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt
  • Patent number: 8884424
    Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: November 11, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt
  • Patent number: 8786062
    Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: July 22, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Chia-Hsiung Hsieh, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh
  • Publication number: 20140151876
    Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.
    Type: Application
    Filed: February 6, 2014
    Publication date: June 5, 2014
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Chia-Hsiung Hsieh, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh
  • Publication number: 20140021636
    Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.
    Type: Application
    Filed: September 23, 2013
    Publication date: January 23, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt