Patents by Inventor Shih-Kuang Chiu

Shih-Kuang Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150041969
    Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed.
    Type: Application
    Filed: November 7, 2013
    Publication date: February 12, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Hong-Da Chang, Yi-Che Lai, Chi-Hsin Chiu, Shih-Kuang Chiu
  • Publication number: 20150035163
    Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced.
    Type: Application
    Filed: August 28, 2013
    Publication date: February 5, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Guang-Hwa Ma, Shih-Kuang Chiu, Shih-Ching Chen, Chun-Chi Ke, Chang-Lun Lu, Chun-Hung Lu, Hsien-Wen Chen, Chun-Tang Lin, Yi-Che Lai, Chi-Hsin Chiu, Wen-Tsung Tseng, Tsung-Te Yuan, Lu-Yi Chen, Mao-Hua Yeh
  • Publication number: 20150035164
    Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.
    Type: Application
    Filed: August 28, 2013
    Publication date: February 5, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Guang-Hwa Ma, Shih-Kuang Chiu, Shih-Ching Chen, Chun-Chi Ke, Chang-Lun Lu, Chun-Hung Lu, Hsien-Wen Chen, Chun-Tang Lin, Yi-Che Lai, Chi-Hsin Chiu, Wen-Tsung Tseng, Tsung-Te Yuan, Lu-Yi Chen, Mao-Hua Yeh
  • Publication number: 20140342507
    Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventors: Yan-Heng Chen, Jung-Pang Huang, Hsin-Yi Liao, Shih-Kuang Chiu, Guang-Hwa Ma
  • Publication number: 20140252603
    Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.
    Type: Application
    Filed: October 17, 2013
    Publication date: September 11, 2014
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Meng-Tsung Lee, Yi-Che Lai, Shih-Kuang Chiu
  • Patent number: 8829672
    Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: September 9, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yan-Heng Chen, Jung-Pang Huang, Hsin-Yi Liao, Shih-Kuang Chiu, Guang-Hwa Ma
  • Publication number: 20140154842
    Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.
    Type: Application
    Filed: February 7, 2014
    Publication date: June 5, 2014
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
  • Patent number: 8741693
    Abstract: A package structure includes a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires. The package structure is easier to accurately control the location of an external electrical contact, and the compatibility of the manufacturing procedures is high.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: June 3, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-An Huang, Hsin-Yi Liao, Shih-Kuang Chiu
  • Publication number: 20140134797
    Abstract: A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a carrier having a release layer and an adhesive layer sequentially formed thereon; disposing a plurality of semiconductor chips on the adhesive layer; forming an encapsulant on the adhesive layer for encapsulating the semiconductor chips; disposing a substrate on the encapsulant; exposing the release layer to light through the carrier so as to remove the release layer and the carrier; and then removing the adhesive layer, thereby effectively preventing the semiconductor chips from being exposed to light so as to avoid any photo damage to the semiconductor chips.
    Type: Application
    Filed: August 29, 2013
    Publication date: May 15, 2014
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chieh-Yuan Chi, Jung-Pang Huang, Yan-Heng Chen, Hsi-Chang Hsu, Chiang-Cheng Chang, Shih-Kuang Chiu
  • Patent number: 8680692
    Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: March 25, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
  • Publication number: 20140080242
    Abstract: A package structure includes a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires. The package structure is easier to accurately control the location of an external electrical contact, and the compatibility of the manufacturing procedures is high.
    Type: Application
    Filed: November 13, 2013
    Publication date: March 20, 2014
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-An Huang, Hsin-Yi Liao, Shih-Kuang Chiu
  • Patent number: 8653661
    Abstract: A package structure having an MEMS element is provided, which includes: a protection layer having openings formed therein; conductors formed in the openings, respectively; conductive pads formed on the protection layer and the conductors; a MEMS chip disposed on the conductive pads; and an encapsulant formed on the protection layer for encapsulating the MEMS chip. By disposing the MEMS chip directly on the protection layer to dispense with the need for a carrier, such as a wafer or a circuit board that would undesirably add to the thickness, the present invention reduces the overall thickness of the package to thereby achieve miniaturization.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: February 18, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Yueh Chan, Chien-Ping Huang, Chun-Chi Ke, Shih-Kuang Chiu
  • Publication number: 20140021629
    Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.
    Type: Application
    Filed: October 18, 2012
    Publication date: January 23, 2014
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu, Fu-Tang Huang
  • Patent number: 8633048
    Abstract: A fabrication method of a package structure having MEMS elements includes: disposing a plate on top of a wafer having MEMS elements and second alignment keys; cutting the plate to form therein a plurality of openings exposing the second alignment keys; performing a wire bonding process and disposing block bodies corresponding to the second alignment keys, respectively; forming an encapsulant and partially removing the encapsulant and the block bodies from the top of the encapsulant; and aligning through the second alignment keys so as to form on the encapsulant a plurality of metal traces. The present invention eliminates the need to form through holes in a silicon substrate as in the prior art so as to reduce the fabrication costs. Further, since the plate only covers the MEMS elements and the encapsulant is partially removed, the overall thickness and size of the package structure are reduced.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: January 21, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chen-Han Lin, Hong-Da Chang, Cheng-Hsiang Liu, Hsin-Yi Liao, Shih-Kuang Chiu
  • Publication number: 20140015125
    Abstract: A method of fabricating a semiconductor package is provided, including: providing a carrier having a plurality of chip areas defined thereon, and forming a connection unit on each of the chip areas; disposing a semiconductor element on each of the connection units; forming an insulating layer on the carrier and the semiconductor elements; and forming on the insulating layer a circuit layer electrically connected to the semiconductor elements. Since being formed only on the chip areas instead of on the overall carrier as in the prior art, the connection units are prevented from expanding or contracting during temperature cycle, thereby avoiding positional deviations of the semiconductor elements.
    Type: Application
    Filed: October 24, 2012
    Publication date: January 16, 2014
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Meng-Tsung Lee, Chiang-Cheng Chang, Shih-Kuang Chiu
  • Publication number: 20130341774
    Abstract: A semiconductor package is provided, including: an insulating layer; a semiconductor element embedded in the insulating layer; an adhesive body embedded in the insulating layer, wherein a portion of the semiconductor element is embedded in the adhesive body; a patterned metal layer embedded in the adhesive body and electrically connected to the semiconductor element; and a redistribution structure formed on the insulating layer and electrically connected to the patterned metal layer. By embedding the semiconductor element in the adhesive body, the present invention can securely fix the semiconductor element at a predetermined position without any positional deviation, thereby improving the product yield.
    Type: Application
    Filed: September 27, 2012
    Publication date: December 26, 2013
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Shih-Kuang Chiu
  • Patent number: 8610272
    Abstract: A package structure includes a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires. The package structure is easier to accurately control the location of an external electrical contact, and the compatibility of the manufacturing procedures is high.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: December 17, 2013
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-An Huang, Hsin-Yi Liao, Shih-Kuang Chiu
  • Publication number: 20130256875
    Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.
    Type: Application
    Filed: July 31, 2012
    Publication date: October 3, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yan-Heng Chen, Jung-Pang Huang, Hsin-Yi Liao, Shih-Kuang Chiu, Guang-Hwa Ma
  • Publication number: 20130249589
    Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 26, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
  • Publication number: 20130228915
    Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.
    Type: Application
    Filed: June 27, 2012
    Publication date: September 5, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu