Patents by Inventor Shih-Kuei Ma

Shih-Kuei Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160172436
    Abstract: Provided is a termination structure including a substrate of a first conductivity type, an epitaxial layer of the first conductivity type, a single bulk isolation structure and a bulk doped region of a second conductivity type. The epitaxial layer is disposed on the substrate. The single bulk isolation structure is disposed on the epitaxial layer. The bulk doped region is disposed in the epitaxial layer below the single bulk isolation structure, wherein the doping depth of the bulk doped region has a gradient distribution. A method of forming a termination structure and a semiconductor device having the termination structure are also provided.
    Type: Application
    Filed: June 25, 2015
    Publication date: June 16, 2016
    Inventors: Geng-Tai Ho, Shih-Kuei Ma, Tien-Chun Lee, Meng-Hung Chen, Hsiao-Chia Wu
  • Publication number: 20160005858
    Abstract: A reduced surface field (RESURF) structure and a lateral diffused metal oxide semiconductor (LDMOS) device including the same are provided. The RESURF structure includes a substrate of a first conductivity type, a well region of a second conductivity type, an isolation structure and a PN junction diode. The well region is disposed in the substrate. The isolation structure is disposed on the well region. The PN junction diode is disposed on the isolation structure and configured to reduce the surface field.
    Type: Application
    Filed: October 29, 2014
    Publication date: January 7, 2016
    Inventors: Shih-Kuei Ma, Geng-Tai Ho
  • Patent number: 8237223
    Abstract: A semiconductor device including a substrate, an epitaxial layer, a first sinker, a transistor, a diode unit, a first buried layer, and a second buried layer is provided. When the semiconductor device is operated at the high voltage, the highly large substrate current due to the external load is avoided through the diode unit disposed in the semiconductor device of an embodiment consistent with the invention. Furthermore, according to the design of the semiconductor device, the issue of the narrow input voltage range is improved, and interference of the semiconductor device with the other semiconductor devices is prevented.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: August 7, 2012
    Assignee: Episil Technologies Inc.
    Inventors: Shih-Kuei Ma, Ta-Chuan Kuo
  • Publication number: 20110057262
    Abstract: A semiconductor device including a substrate, an epitaxial layer, a first sinker, a transistor, a diode unit, a first buried layer, and a second buried layer is provided. When the semiconductor device is operated at the high voltage, the highly large substrate current due to the external load is avoided through the diode unit disposed in the semiconductor device of an embodiment consistent with the invention. Furthermore, according to the design of the semiconductor device, the issue of the narrow input voltage range is improved, and interference of the semiconductor device with the other semiconductor devices is prevented.
    Type: Application
    Filed: September 10, 2009
    Publication date: March 10, 2011
    Applicant: EPISIL TECHNOLOGIES INC.
    Inventors: Shih-Kuei Ma, Ta-Chuan Kuo
  • Patent number: 7538396
    Abstract: A semiconductor device includes a substrate, an epitaxial layer, a sinker, an active device, a first buried layer, and a second buried layer. The substrate has a first type conductivity. The epitaxial layer has a second type conductivity, and is located on the substrate. The sinker has the second type conductivity, and is located in the epitaxial layer. The sinker extends from the substrate to an upper surface of the epitaxial layer, and partitions a region off from the epitaxial layer. The active device is located within the region. The first buried layer has the first type conductivity, and is located between the region and the substrate. The second buried layer has the second type conductivity, and is located between the first buried layer and the substrate. The second buried layer connects with the sinker. Because of the above-mentioned configuration, latch-up can be prevented.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: May 26, 2009
    Assignee: Episil Technologies Inc.
    Inventors: Shih-Kuei Ma, Chung-Yeh Lee, Chun-Ying Yeh, Wei-Ting Kuo
  • Patent number: 7514754
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: April 7, 2009
    Assignee: Episil Technologies Inc.
    Inventors: Shih-Kuei Ma, Chung-Yeh Lee, Chun-Ying Yeh, Ker-Hsiao Huo
  • Patent number: 7411271
    Abstract: A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second sinker, a first buried layer and a second buried layer. The first and the second epitaxial layer are sequentially disposed on the substrate. The first sinker and the first buried layer separate a first region from the second epitaxial layer. The second sinker and the second buried layer separate a second region from the second epitaxial layer. The well is disposed in the first region. A first transistor is disposed in the well. A second transistor is disposed in the second region. A deep trench isolation is disposed between the first and the second region and extends from the substrate to the upper surface of the second epitaxial layer.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: August 12, 2008
    Assignee: Episil Technologies Inc.
    Inventors: Shih-Kuei Ma, Chung-Yeh Lee, Chun-Ying Yeh, Shin-Cheng Lin
  • Publication number: 20080173951
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 24, 2008
    Applicant: EPISIL TECHNOLOGIES INC.
    Inventors: Shih-Kuei Ma, Chung-Yeh Lee, Chun-Ying Yeh, Ker-Hsiao Huo
  • Publication number: 20080173948
    Abstract: A semiconductor device includes a substrate, an epitaxial layer, a sinker, an active device, a first buried layer, and a second buried layer. The substrate has a first type conductivity. The epitaxial layer has a second type conductivity, and is located on the substrate. The sinker has the second type conductivity, and is located in the epitaxial layer. The sinker extends from the substrate to an upper surface of the epitaxial layer, and partitions a region off from the epitaxial layer. The active device is located within the region. The first buried layer has the first type conductivity, and is located between the region and the substrate. The second buried layer has the second type conductivity, and is located between the first buried layer and the substrate. The second buried layer connects with the sinker. Because of the above-mentioned configuration, latch-up can be prevented.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 24, 2008
    Applicant: EPISIL TECHNOLOGIES INC.
    Inventors: Shih-Kuei Ma, Chung-Yeh Lee, Chun-Ying Yeh, Wei-Ting Kuo
  • Publication number: 20080173949
    Abstract: A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second sinker, a first buried layer and a second buried layer. The first and the second epitaxial layer are sequentially disposed on the substrate. The first sinker and the first buried layer separate a first region from the second epitaxial layer. The second sinker and the second buried layer separate a second region from the second epitaxial layer. The well is disposed in the first region. A first transistor is disposed in the well. A second transistor is disposed in the second region. A deep trench isolation is disposed between the first and the second region and extends from the substrate to the upper surface of the second epitaxial layer.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 24, 2008
    Applicant: EPISIL TECHNOLOGIES INC.
    Inventors: Shih-Kuei Ma, Chung-Yeh Lee, Chun-Ying Yeh, Shin-Cheng Lin