Patents by Inventor Shih-Lien Linus Lu

Shih-Lien Linus Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210314175
    Abstract: A PUF generator includes a difference generator circuit with first and second transistors having a first predetermined VT. The difference generator circuit is configured to provide a first output signal for generating a PUF signature based on respective turn on times of the first and second transistors. An amplifier includes a plurality of transistors having a second predetermined VT. The amplifier is configured to receive the first output signal and output the PUF signature.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Inventors: Shih-Lien Linus Lu, Jui-Che Tsai, Cheng-En Lee
  • Patent number: 11138125
    Abstract: A method for controlling a cache comprising receiving a request for data and determining whether the requested data is present in a first portion of the cache, a second portion of cache, or not in the cache. If the requested data is not located in the MRU portion of the cache, moving the data into the first portion of the cache.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Shih-Lien Linus Lu
  • Publication number: 20210306148
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Application
    Filed: November 30, 2020
    Publication date: September 30, 2021
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Publication number: 20210296151
    Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Shih-Lien Linus Lu, Cormac Michael O'Connell
  • Publication number: 20210287738
    Abstract: A circuit includes a memory array, a control circuit configured to identify an address of a first row containing a weak cell, and store corresponding address information in a storage device, and an address decoding circuit including NAND pairs, inverter pairs, and a logic tree. Each NAND pair receives corresponding bits of the address information and the address of the first row and corresponding inverted bits of the address information and the address of the first row inverted by corresponding inverter pairs, and output terminals of the NAND pairs are connected to the logic tree. The logic tree matches the address information with the address of the first row based on output logic levels from the NAND pairs and, in response to the corresponding address information matching the address of the first row, activates a second row of the memory array simultaneously with the first row being activated.
    Type: Application
    Filed: May 27, 2021
    Publication date: September 16, 2021
    Inventor: Shih-Lien Linus LU
  • Publication number: 20210271417
    Abstract: A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.
    Type: Application
    Filed: August 5, 2020
    Publication date: September 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hiroki Noguchi, Shih-Lien Linus Lu, Yu-Der Chih, Yih Wang
  • Patent number: 11108572
    Abstract: A physically unclonable function (PUF) device is provided. The PUF device includes: a plurality of PUF cells configured to generate an output. Each of the plurality of cells includes a sense amplifier, a load circuit. The sense amplifier includes a first circuit and a second circuit configured to generate a bit line and a complementary bit line. The sense amplifier having a first circuit and a second circuit configured to generate a bit line and a complementary bit line. The first circuit generates an output at a first output node and the second circuit generates an output at the second output node. The load circuit having a first transistor and a second transistor configured to generate a bias to the sense amplifier to obtain a mask bit at a first output node and a second output node. The control terminal of the first transistor is controlled by a first selection bit, and a control terminal of the second transistor is controlled by a second selection bit.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shih-Lien Linus Lu
  • Publication number: 20210262865
    Abstract: A temperature-sensing device configured to monitor a temperature is disclosed. The temperature-sensing device includes: a first capacitor comprising a first oxide layer with a first thickness; a second capacitor comprising a second oxide layer with a second thickness, wherein the second thickness of the second oxide layer is different from the first thickness of the first oxide layer; and a control logic circuit, coupled to the first and second capacitors, and configured to determine whether the monitored temperature is equal to or greater than a threshold temperature based on whether at least one of the first and second oxide layers breaks down.
    Type: Application
    Filed: May 11, 2021
    Publication date: August 26, 2021
    Inventor: Shih-Lien Linus LU
  • Publication number: 20210248275
    Abstract: Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. One or more activation signals are provided to a PUF cell under a plurality of conditions. A PUF cell output provided by the PUF cell under each of the plurality of conditions is determined. A determination is made of a number of times the PUF cell output of the PUF cell is consistent. And a device classification value is determined based on the determined number of times for a plurality of PUF cells.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Inventors: Cheng-En Lee, Shih-Lien Linus Lu
  • Publication number: 20210250187
    Abstract: Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. A first signal is provided to a first branch of a PUF cell and a second signal is provided to a second branch of the PUF cell, the first and second signals being provided in synchronization. A base PUF cell value is determined based on an output of the PUF cell produced by the first signal and the second signal. A third signal is provided to the first branch and a fourth signal is provided to the second branch, the third signal and fourth signal being provided out of synchronization. A stressed PUF cell value is determined based on an output of the PUF cell produced by the third signal and the fourth signal. The PUF cell is determined to be unusable based on a difference between the PUF cell value and the stressed PUF cell value.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Inventors: Shih-Lien Linus Lu, Cheng-En Lee
  • Patent number: 11082242
    Abstract: An integrated circuit is fabricated using a semiconductor fabrication process. One or more uncontrollable random physical processes in the semiconductor fabrication process can cause small differences between the integrated circuit and other similarly designed integrated circuit. These small differences can cause transistors of the integrated circuit to have different threshold voltages. The integrated circuit can use these different threshold voltages to quantify its physical uniqueness to differentiate itself from other integrated circuits similarly designed and fabricated by the semiconductor fabrication process.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: August 3, 2021
    Inventor: Shih-Lien Linus Lu
  • Publication number: 20210233587
    Abstract: An efficient FeFET-based CAM is disclosed which is capable of performing normal read, write but has the ability to match input data with don't-care. More specifically, a Ferroelectric FET Based Ternary Content Addressable Memory is disclosed. The design in some examples utilizes two FeFETs and four MOSFETs per cell. The CAM can be written in columns through multi-phase writes. It can be used a normal memory with indexing read. It also has the ability for ternary content-based search. The don't-care values can be either the input or the stored data.
    Type: Application
    Filed: November 24, 2020
    Publication date: July 29, 2021
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11073428
    Abstract: A temperature-sensing device configured to monitor a temperature includes: a first conductive line; a second conductive line, wherein the first and second conductive lines have respective different cross-sectional dimensions; a sensing circuit, coupled to the first and second conductive lines, and configured to determine a logic state of an output signal based on a difference between respective signal levels present on the first and second conductive lines; and a control circuit, coupled to the sensing circuit, and configured to determine whether the monitored temperature is above or below a pre-defined threshold temperature based on the determined logic state.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Ming-Hsien Lin, Anthony Oates
  • Publication number: 20210224193
    Abstract: An integrated circuit (IC) is provided. The IC includes a cache memory divided into a plurality of groups and an address decoder. The groups are assigned in rotation for a plurality of time periods. Each group is assigned in a corresponding single one of the time periods. The address decoder is configured to obtain a set address according to an access address and provide a physical address according to the set address. When the access address corresponds to a first group, the physical address is different from the set address. When the access address corresponds to the groups other than the first group, the physical address is the same as the set address. The sets of the first group that is assigned in a first time period are not overlapping with the sets of other first groups assigned in the time periods other than the first time period.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shih-Lien Linus LU
  • Publication number: 20210226806
    Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventors: Jui-Che TSAI, Shih-Lien Linus LU, Cheng Hung LEE, Chia-En HUANG
  • Publication number: 20210218583
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) generator. Unstable bits of the plurality of key bits are identified, and a security key is generated based on the plurality of key bits, wherein the security key excludes the identified unstable bits.
    Type: Application
    Filed: March 29, 2021
    Publication date: July 15, 2021
    Inventors: Saman M.I. Adham, Shih-Lien Linus Lu, Peter Noel
  • Publication number: 20210211312
    Abstract: Disclosed is a physical unclonable function generator circuit and method.
    Type: Application
    Filed: March 22, 2021
    Publication date: July 8, 2021
    Inventors: Shih-Lien Linus LU, Chen-En Lee
  • Publication number: 20210202467
    Abstract: A memory cell array includes a first and second memory cell, a first and second word line and a first bit line. The first memory cell is in a first row in a first direction. The second memory cell is in a second row in the first direction, and is separated from the first memory cell in a second direction. The first word line extends in the first direction and is coupled to the first memory cell. The second word line extends in the first direction and is coupled to the second memory cell. The first bit line extends in the second direction and is coupled to the first and second memory cell. The first memory cell corresponds to a five transistor memory cell. The first memory cell includes a first active region having a first length, and a second active region having a second length.
    Type: Application
    Filed: March 12, 2021
    Publication date: July 1, 2021
    Inventor: Shih-Lien Linus LU
  • Patent number: 11049555
    Abstract: A memory device includes a plurality of bit lines, a plurality of word lines, and a memory cell array including a plurality of bit cells coupled to the bit lines and the word lines. Each of the bit cells is configured to present an initial logic state on the bit lines. A power supply terminal is coupled to the memory cell array. A controller is coupled to the word lines and the bit lines, and is configured to, during a RNG phase, precharge the bit lines to a second voltage level lower than a first voltage level, and determine the initial logic states of the plurality of bit cells to generate a random number. The first voltage level is a voltage level for operating the memory cell array during an SRAM phase.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Che Tsai, Chen-Lin Yang, Yu-Hao Hsu, Shih-Lien Linus Lu
  • Publication number: 20210191813
    Abstract: A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a generation matrix; transforming the generating matrix into a systematic form, wherein the transformed generating matrix is composed of a parity matrix and a check matrix; sorting rows of the parity matrix according to row weights; determining a number of rows in the parity matrix to be truncated; generating a truncated parity matrix by keeping the sorted rows of the P matrix that have weights less than or equal to weights of the truncated rows of the P matrix so as to minimize a number of logic gate operations; and forming an error correction circuit with the number of logic gate operations minimized according to the truncated P matrix to correct the error of the codeword.
    Type: Application
    Filed: March 5, 2021
    Publication date: June 24, 2021
    Inventor: SHIH-LIEN LINUS LU