Patents by Inventor Shih-Lien Linus Lu

Shih-Lien Linus Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087624
    Abstract: Disclosed herein are related to operating a memory system including memory banks and buffers. Each buffer may perform a write process to write data to a corresponding memory bank. In one aspect, the memory system includes a buffer controller including a queue register, a first pointer register, a second pointer register, and a queue controller. In one aspect, the queue register includes entries, where each entry may store an address of a corresponding memory bank. The first pointer register may indicate a first entry storing an address of a memory bank, on which the write process is predicted to be completed next. The second pointer register may indicate a second entry to be updated. The queue controller may configure the queue register according to the first pointer register and the second pointer register, and configure one or more buffers to perform the write process, according to the entries.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shih-Lien Linus Lu
  • Publication number: 20240089126
    Abstract: The present disclosure describes embodiments of a device with memory and a processor. The memory is configured to store integrated circuit (IC) trim and redundancy information. The processor is configured to extract bits from the IC trim and redundancy information, perform a hashing function on the extracted bits to generate hashed bits, and in response to statistical properties of the hashed bits meeting one or more criteria, output the hashed bits. In some embodiments, the memory that stores the IC trim and redundancy information can be different from other memory used by the device for other operations (e.g., accessing user data and program data that have been written into system memory).
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Katherine H. Chiang, Shih-Lien Linus Lu
  • Publication number: 20240089127
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) generator. Unstable bits of the plurality of key bits are identified, and a security key is generated based on the plurality of key bits, wherein the security key excludes the identified unstable bits.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Saman M.I. Adham, Shih-Lien Linus Lu, Peter Noel
  • Publication number: 20240079257
    Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits.
    Type: Application
    Filed: April 26, 2023
    Publication date: March 7, 2024
    Inventors: Shih-Lien Linus LU, Cormac Michael O'CONNELL
  • Publication number: 20240071957
    Abstract: An integrated circuit layout is provided. The integrated circuit layout includes: a first active region having a first plurality of field effect transistors (FETs); and an interconnect contacting sources and drains of the first plurality of FETs in the first active region through a first set of contact structures. At least one of the first set of contact structures is electrically non-conductive.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11915787
    Abstract: An integrated circuit (IC) device includes a substrate, and a memory array layer having a plurality of transistors. First through fourth gate contacts are arranged along a first axis, and coupled to underlying gates of the plurality of transistors. First through fifth source/drain contacts in the memory array layer extend along a second axis transverse to the first axis, and are coupled to underlying source/drains of the plurality of transistors. The gate contacts and the source/drain contacts are alternatingly arranged along the first axis. A source line extends along the first axis, and is coupled to the first and fifth source/drain contacts. First and second word lines extend along the first axis, the first word line is coupled to the first and third gate contacts, and the second word line is coupled to the second and fourth gate contacts.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Feng Young, Yu-Ming Lin, Shih-Lien Linus Lu, Han-Jong Chia, Sai-Hooi Yeong, Chia-En Huang, Yih Wang
  • Patent number: 11908505
    Abstract: An efficient FeFET-based CAM is disclosed which is capable of performing normal read, write but has the ability to match input data with don't-care. More specifically, a Ferroelectric FET Based Ternary Content Addressable Memory is disclosed. The design in some examples utilizes two FeFETs and four MOSFETs per cell. The CAM can be written in columns through multi-phase writes. It can be used a normal memory with indexing read. It also has the ability for ternary content-based search. The don't-care values can be either the input or the stored data.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11902455
    Abstract: Disclosed is a physical unclonable function generator circuit and method.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Cheng-En Lee
  • Patent number: 11899828
    Abstract: Methods and apparatus for protecting a physical unclonable function (PUF) generator are disclosed. In one example, a PUF generator is disclosed. The PUF generator includes a PUF cell array, a PUF control circuit and a reset circuit. The PUF cell array comprises a plurality of bit cells. Each of the plurality of bit cells is configurable into at least two different stable states. The PUF control circuit is coupled to the PUF cell array and is configured to access each of the plurality of bit cells to determine one of the at least two different stable states upon a power-up of the plurality of bit cells, and generate a PUF signature based on the determined stable states of the plurality of bit cells. The reset circuit is coupled to the PUF cell array and is configured to set the plurality of bit cells to represent their initialization data based on an indication of a voltage tempering event of a supply voltage of the PUF cell array.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Lien Linus Lu
  • Publication number: 20240013828
    Abstract: A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 11, 2024
    Inventors: SHIH-LIEN LINUS LU, FONG-YUAN CHANG, YI-CHUN SHIH
  • Patent number: 11862292
    Abstract: Disclosed herein are related to operating a memory system including memory banks and buffers. Each buffer may perform a write process to write data to a corresponding memory bank. In one aspect, the memory system includes a buffer controller including a queue register, a first pointer register, a second pointer register, and a queue controller. In one aspect, the queue register includes entries, where each entry may store an address of a corresponding memory bank. The first pointer register may indicate a first entry storing an address of a memory bank, on which the write process is predicted to be completed next. The second pointer register may indicate a second entry to be updated. The queue controller may configure the queue register according to the first pointer register and the second pointer register, and configure one or more buffers to perform the write process, according to the entries.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Shih-LIen Linus Lu
  • Patent number: 11856115
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) generator. Unstable bits of the plurality of key bits are identified, and a security key is generated based on the plurality of key bits, wherein the security key excludes the identified unstable bits.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Saman M. I. Adham, Shih-Lien Linus Lu, Peter Noel
  • Patent number: 11856116
    Abstract: Disclosed is a device and method to secure software update information for authorized entities. In one embodiment, a device for receiving secured software update information from a server, the device includes: a physical unclonable function (PUF) information generator, comprising a PUF cell array, configured to generate PUF information, wherein the PUF information comprises at least one PUF response output, wherein the at least one PUF response output is used to encrypt the software update information on the server so as to generate encrypted software update information; a first encrypter, configured to encrypt the PUF information from the PUF information generator using one of at least one public key from the server so as to generate encrypted PUF information; and a second encrypter, configured to decrypt the encrypted software update information using one of the at least one PUF response output so as to obtain the software update information.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11856114
    Abstract: The present disclosure describes embodiments of a device with memory and a processor. The memory is configured to store integrated circuit (IC) trim and redundancy information. The processor is configured to extract bits from the IC trim and redundancy information, perform a hashing function on the extracted bits to generate hashed bits, and in response to statistical properties of the hashed bits meeting one or more criteria, output the hashed bits. In some embodiments, the memory that stores the IC trim and redundancy information can be different from other memory used by the device for other operations (e.g., accessing user data and program data that have been written into system memory).
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Katherine H. Chiang, Shih-Lien Linus Lu
  • Publication number: 20230385459
    Abstract: Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. One or more activation signals are provided to a PUF cell under a plurality of conditions. A PUF cell output provided by the PUF cell under each of the plurality of conditions is determined. A determination is made of a number of times the PUF cell output of the PUF cell is consistent. And a device classification value is determined based on the determined number of times for a plurality of PUF cells.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Cheng-En Lee, Shih-Lien Linus Lu
  • Publication number: 20230384171
    Abstract: A temperature-sensing device configured to monitor a temperature is disclosed. The temperature-sensing device includes: a first capacitor comprising a first oxide layer with a first thickness; a second capacitor comprising a second oxide layer with a second thickness, wherein the second thickness of the second oxide layer is different from the first thickness of the first oxide layer; and a control logic circuit, coupled to the first and second capacitors, and configured to determine whether the monitored temperature is equal to or greater than a threshold temperature based on whether at least one of the first and second oxide layers breaks down.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventor: Shih-Lien Linus LU
  • Publication number: 20230385145
    Abstract: A memory circuit includes: a memory configured to store a data unit and parity bits, the parity bits including data parity bits based on the data unit and write address parity bits based on a write address associated with the stored data unit; a write address port configured to receive the write address for the stored data unit; a first decoding circuit configured to determine when a data error exists based on the stored data unit and the data parity bits; a second decoding circuit configured to generate a decoded write address from a read address and the write address parity bits; and an error detecting circuit configured to determine when an address error exists based on a comparison of the decoded write address to the read address.
    Type: Application
    Filed: July 19, 2023
    Publication date: November 30, 2023
    Inventors: Saman M. I. ADHAM, Ramin SHARIAT-YAZDI, Shih-Lien Linus LU
  • Publication number: 20230388135
    Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Shih-Lien Linus LU, Cormac Michael O'Connell
  • Publication number: 20230376378
    Abstract: An integrated circuit includes a first set of inverters configured to receive a first set of check bits, and to generate a second set of check bits, a first memory cell array including a first portion of memory cells configured to store a first set of data, and a second portion of memory cells configured to store the second set of check bits, a second set of inverters to receive a third set of check bits, and to generate a fourth set of check bits, and an error correction code decoder configured to detect or correct an error in a second set of data or the fourth set of check bits thereby generating a set of output data and a been-attacked signal. The second set of data corresponds to the first set of data. The been-attacked signal indicates a reset attack by a user.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventor: Shih-Lien Linus LU
  • Publication number: 20230377671
    Abstract: A method of testing a three dimensional (3D) memory cell array includes writing data to each layer of memory cells in the 3D memory cell array, simultaneously performing a read operation of each memory cell in at least a first pillar of the 3D memory cell array, determining whether a memory cell in the 3D memory cell array has failed in response to the read operation, and replacing at least one failed memory cell in the 3D memory cell array with a spare memory cell in response to determining that the memory cell in the 3D memory cell array has failed. The first pillar includes memory cells on each corresponding layer of the 3D memory cell array.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Chao-I WU, Shih-Lien Linus LU, Sai-Hooi YEONG