Abstract: A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Abstract: A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.

Abstract: In a method of manufacturing a semiconductor device, a first conductive pattern and a second conductive pattern are formed over the first conductive pattern, in a first interlayer dielectric (ILD) layer disposed over a substrate. The second conductive pattern contacts the first conductive pattern. A space is formed in the first ILD layer by removing a part of the second conductive pattern to expose a part of the first conductive pattern. The space is filled with a dielectric material. A third conductive pattern is formed over a remaining portion of the second conductive pattern. A via contact connecting the first conductive pattern and the third conductive pattern is formed by patterning the remaining portion of the second conductive pattern as an etching mask.

Abstract: A method of generating a layout pattern includes determining a first energy density indirectly exposed to a first feature of one or more features of a layout pattern on an energy-sensitive material when the one or more features of the layout pattern on the energy-sensitive material are directly exposed by a charged particle beam. The method also includes adjusting a second energy density exposed the first feature when the first feature is directly exposed by the charged particle beam. A total energy density of the first feature that comprises a sum of the first energy density from the indirect exposure and the second energy density from the direct exposure is maintained at about a threshold energy level to fully expose the first feature in the energy-sensitive material.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; depositing a mask layer over the substrate; forming a mandrel pattern over the mask layer; forming a spacer pattern around the mandrel pattern; removing the mandrel pattern; and applying at least one directional etching operation along a first direction to etch two opposing ends of the spacer pattern and form a first spacer feature and a second spacer feature apart from each other.

Abstract: An illumination system includes a plurality of pixels (or spots) that are (or may be) configured in one or more polarization configuration types. The pixels of the illumination system may be configured to promote particular types of polarization (e.g., transverse electric (TE) polarization, transvers magnetic (TM) polarization) to increase pattern contrast while achieving suitable exposure operation throughput. Moreover, the pixels of the pixels of the illumination system may be configured to achieve free-form (arbitrary or freely-configurable) polarization, which permits the polarization of radiation to be tailored to particular exposure operation patterns and other parameters.

Abstract: A method of operating a semiconductor apparatus includes generating an air flow that flows from a covering structure; causing a photomask to move over the covering structure such that particles attached to the photomask are blown away from the photomask by the air flow; and irradiating the photomask with light through a light transmission region of the covering structure.

Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Abstract: A mirror structure includes an insulator layer and a first conductive layer disposed on the insulator layer. The first conductive layer includes a first non-conductive film disposed on the insulator layer. The first non-conductive film includes one or more first conductive segments. The mirror structure also includes a reflective layer disposed on the first conductive layer and an electro optical layer disposed on the reflective layer. The mirror structure further includes a second conductive layer disposed on the electro optical layer. The second conductive layer includes a second non-conductive film disposed on the electro optical layer. The second non-conductive film includes one or more second conductive segments.

Abstract: A method of operating a semiconductor apparatus includes generating an electric field in peripheral areas of a first covering structure and a second covering structure; causing a photomask to move to a position between the first and second covering structures such that the photomask at least partially vertically overlaps the first and second covering structures and such that particles attached to the photomask are attracted to the first and second covering structures by the electric field; and irradiating the photomask with light through light transmission regions of the first and second covering structures.

Abstract: A radar monitoring system and a radar monitoring method for monitoring a traffic control zone involve installing two radars near the traffic control zone so that the radars emit radar waves covering the traffic control zone and serve as backups for each other; locating any object in the traffic control zone as a coordinate point with respect to a set of X and Y coordinate axes, and subjecting the X and Y coordinate axes of the two radars to axial normalization, so that an identical object in the traffic control zone is located by the first radar and the second radar at approximately the same coordinate point. An alert area is defined in the traffic control zone and an excluded area around a resident facility in the traffic control zone is excluded from the alert area. When an object in the alert area is determined as an obstacle, an alert is triggered.

Abstract: A method of generating a layout pattern includes determining a first energy density indirectly exposed to a first feature of one or more features of a layout pattern on an energy-sensitive material when the one or more features of the layout pattern on the energy-sensitive material are directly exposed by a charged particle beam. The method also includes adjusting a second energy density exposed the first feature when the first feature is directly exposed by the charged particle beam. A total energy density of the first feature that comprises a sum of the first energy density from the indirect exposure and the second energy density from the direct exposure is maintained at about a threshold energy level to fully expose the first feature in the energy-sensitive material.

Abstract: In one example, an apparatus includes an extreme ultraviolet illumination source and an illuminator. The extreme ultraviolet illumination source is arranged to generate a beam of extreme ultraviolet illumination to pattern a resist layer on a substrate. The illuminator is arranged to direct the beam of extreme ultraviolet illumination onto a surface of a photomask. In one example, the illuminator includes a field facet mirror and a pupil facet mirror. The field facet mirror includes a first plurality of facets arranged to split the beam of extreme ultraviolet illumination into a plurality of light channels. The pupil facet mirror includes a second plurality of facets arranged to direct the plurality of light channels onto the surface of the photomask. The distribution of the second plurality of facets is denser at a periphery of the pupil facet mirror than at a center of the pupil facet mirror.

Abstract: A semiconductor processing system includes a layout database that stores a plurality of layouts indicating features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and determines, for each layout, whether a non-perpendicular particle bombardment process should be utilized in conjunction with a photolithography process for forming the features of the layout in a wafer.

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first spacer over a substrate. The method includes partially removing the first spacer to form a gap dividing the first spacer into a first part and a second part. The method includes forming a filling layer covering a first top surface and a first sidewall of the first spacer. The filling layer and the first spacer together form a strip structure. The method includes forming a second spacer over a second sidewall of the strip structure. The method includes forming a third spacer over a third sidewall of the second spacer. The third spacer is narrower than the second spacer.

Abstract: A method includes generating an electron beam from a radiation source; modifying an energy distribution of the electron beam through a first shaping aperture; and exposing a substrate to portions of the electron beam passing through the first shaping aperture. The first shaping aperture comprises blocking strips with a plurality of slots therebetween, a frame surrounding the blocking strips, and a diagonal support connected to the frame and one of the blocking strips.

Abstract: In a method of manufacturing a semiconductor device, a first conductive layer is formed over a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive layer, a via is formed in the second ILD layer to contact an upper surface of the first conductive layer, a hard mask pattern is formed over the second ILD layer, the second ILD layer and the first conductive layer are patterned by using the hard mask pattern as an etching mask, thereby forming patterned second ILD layers and first wiring patterns, after the patterning, the hard mask pattern is removed, and a third ILD layer is formed between the patterned second ILD layers and the first wiring patterns.

Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.