Patents by Inventor Shih-Ming Chang

Shih-Ming Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9735140
    Abstract: The present disclosure describes methods for transferring a desired layout into a target layer. The method includes a step of forming a spacer, having a second width, around a first and a second desired layout feature pattern of the desired layout over a semiconductor substrate. The first desired layout feature pattern is formed using a first sub-layout and the second desired layout feature pattern is formed using a second sub-layout. The first and second desired layout feature patterns are separated by a first width. The method further includes forming a third desired layout feature pattern according to a third sub-layout. The third desired layout feature pattern is shaped in part by the spacer. The method further includes removing the spacer from around the first and second desired layout feature pattern and etching the target layer using the first, second, and third layout feature patterns as masking features.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 9716032
    Abstract: The present disclosure provides a method for forming a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: July 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Po Tang, Shih-Ming Chang, Ken-Hsien Hsieh, Ru-Gun Liu
  • Patent number: 9711369
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes forming a main pattern on a substrate; forming a spacer on sidewalls of the main pattern; forming a cut pattern having an opening by a first lithography process; and performing a cut process to selectively remove portions of the spacer within the opening of the cut pattern while the main pattern remains unetched, thereby defining a circuit pattern by the main pattern and the spacer. The circuit pattern includes a sharp jog.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shih-Ming Chang
  • Publication number: 20170200584
    Abstract: The present disclosure provides one embodiment of a method that includes slicing a first sub-polygon out of the pattern layout and writing the first sub-polygon onto the substrate using a beam with a first beam setting that is associated with the first sub-polygon. The method additional includes slicing a second sub-polygon out of the remaining pattern layout that does not include the first sub-polygon. The second sub-polygon interfaces with the first sub-polygon on at least one edge. Also, the method includes, without turning off the beam after writing the first sub-polygon onto the substrate, writing the second sub-polygon onto the substrate with a second beam setting that is associated with the second sub-polygon.
    Type: Application
    Filed: January 13, 2016
    Publication date: July 13, 2017
    Inventor: Shih-Ming Chang
  • Patent number: 9697325
    Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Ming-Yo Chung, Tzu-Chun Lo, Ying-Hao Su
  • Patent number: 9684236
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first patterned hard mask over a material layer. The first patterned hard mask defines an opening. The method also includes forming a direct-self-assembly (DSA) layer having a first portion and a second portion within the opening, removing the first portion of the DSA layer, forming spacers along sidewalls of the second portion of the DSA layer and removing the second portion of the DSA layer. The spacers form a second patterned hard mask over the material layer.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ken-Hsien Hsieh, Kuan-Hsin Lo, Shih-Ming Chang, Wei-Liang Lin, Joy Cheng, Chun-Kuang Chen, Ching-Yu Chang, Kuei-Shun Chen, Ru-Gun Liu, Tsai-Sheng Gau, Chin-Hsiang Lin
  • Publication number: 20170170110
    Abstract: A method includes forming a trench that is partially filled with a first metal material, the trench being formed within a first Interlayer Dielectric (ILD) layer, filling a remaining portion of the trench with a sacrificial material, depositing a buffer layer on the first ILD layer, patterning the buffer layer to form a hole within the buffer layer to expose the sacrificial material, and removing the sacrificial material.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Publication number: 20170168385
    Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a first main feature and a second main feature; determining that the first main feature includes has a curvilinear-based shaped; determining that the second main feature has a polygon-based shape; and mapping a first portion of the IC design layout that includes the first main feature onto a polar coordinate and mapping a second portion of the IC design layout that includes the second main feature on onto a Cartesian coordinate.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Inventor: SHIH-MING CHANG
  • Publication number: 20170161740
    Abstract: The present disclosure provides a system and a method for cash flow verification by a third-party payment platform. The system includes a server and a client device. The client device includes a network device, a storage device and a processor. The storage device is configured to store a plurality of programmed instructions and establish a client database. The processor is configured to execute the programmed instructions to generate execution history data, wherein the execution history data comprises cash flow history data, which can be produced by a third-party platform. While the network device is incapable of connecting the server through the Internet, the processor stores the execution history data in the client database; while the network device is capable of connecting the server through the Internet, the processor transmits the execution history data to the server through the network device for verification, and the verification comprises cash flow verification.
    Type: Application
    Filed: March 29, 2016
    Publication date: June 8, 2017
    Inventors: Jia-Wei YANG, Shih-Ming CHANG
  • Patent number: 9672320
    Abstract: A method of manufacturing an integrated circuit (IC) includes: receiving a target layout of the IC, decomposing the target layout into a plurality of sub-layouts for a multiple patterning process, identifying re-locatable pattern edges in the sub-layouts, and relocating the edges to improve manufacturability of the IC. In an embodiment, relocating the edges includes: choosing an evaluation index based on a target manufacturing process, moving one or more of the edges, calculating a score of manufacturability based on the evaluation index, and repeating the moving and the calculating until the score meets a threshold.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: June 6, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chien-Fu Lee, Chin-Yuan Tseng
  • Publication number: 20170147735
    Abstract: Provided is a method of fabricating a semiconductor device. An integrated circuit (IC) layout plan is obtained, The IC layout plan contains critical features and non-critical features. Locational information regarding a defect on a blank reticle is obtained. The blank reticle is a candidate reticle for being patterned with the IC layout plan. Based on the locational information regarding the defect and the IC layout plan, a determination is made that at some of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan, regardless of whether the IC layout plan is globally manipulated or not before being patterned onto the blank reticle. In response to the determination, selected local portions of the IC layout plan are re-arranged such that none of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan.
    Type: Application
    Filed: February 8, 2017
    Publication date: May 25, 2017
    Inventors: Shih-Ming Chang, Chia-Hao Yu
  • Publication number: 20170124243
    Abstract: An integrated circuit device includes first and second features, each including an end portion arranged along a common axis, and separated by a space. The end portion of the first feature includes a first indention adjacent to the space. The end portion of the second feature includes a first indention adjacent to the space, mirroring the first indention of the first feature about the space. The end portions are substantially similar in shape.
    Type: Application
    Filed: November 21, 2016
    Publication date: May 4, 2017
    Inventors: Shih-Ming Chang, Kuei-Liang Lu
  • Publication number: 20170108787
    Abstract: A system and method is provided for providing a thermal distribution on a workpiece during a lithographic process. The system provides a source of lithographic energy to workpiece, such as a workpiece having a lithographic film formed thereover. A workpiece support having a plurality of thermal devices embedded therein is configured to support the workpiece concurrent to an exposure of the workpiece to the lithographic energy. A controller individually controls a temperature of each of the plurality of thermal devices, therein controlling a specified temperature distribution across the workpiece associated with the exposure of the workpiece to the lithographic energy. Controlling the temperature of the thermal devices can be based on a model, a measured temperature of the workpiece, and/or a prediction of a temperature at one or more locations on the workpiece.
    Type: Application
    Filed: December 27, 2016
    Publication date: April 20, 2017
    Inventor: Shih-Ming Chang
  • Patent number: 9627310
    Abstract: A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: April 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Tsong-Hua Ou, Ru-Gun Liu, Fang-Yu Fan, Yuan-Te Hou
  • Publication number: 20170069505
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 9, 2017
    Inventors: RU-GUN LIU, CHENG-HSIUNG TSAI, CHUNG-JU LEE, CHIH-MING LAI, CHIA-YING LEE, JYU-HORNG SHIEH, KEN-HSIEN HSIEH, MING-FENG SHIEH, SHAU-LIN SHUE, SHIH-MING CHANG, TIEN-I BAO, TSAI-SHENG GAU
  • Patent number: 9581900
    Abstract: A method for using self aligned multiple patterning with multiple resist layers includes forming a first patterned resist layer onto a substrate, forming a spacer layer on top of the first patterned resist layer such that spacer forms on side walls of features of the first resist layer, and forming a second patterned resist layer over the spacer layer and depositing a masking layer. The method further includes performing a planarizing process to expose the first patterned resist layer, removing the first resist layer, removing the second resist layer, and exposing the substrate.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Chih-Ming Lai, Ken-Hsien Hsieh, Ru-Gun Liu, Shih-Ming Chang
  • Publication number: 20170053870
    Abstract: A device includes a substrate feature disposed over a substrate. The substrate feature has a first length extending along a first direction and a second length extending along a second direction. The first length is greater than the second length. The device also includes a first material feature disposed over the substrate. The first material feature has a first surface in physical contact with the substrate feature and a second surface opposite to the first surface. The first surface has a third length extending along the first direction and a fourth length extending along the second direction. The third length is greater than the fourth length. The second surface has a fifth length extending along the first direction and a sixth length extending along the second direction. The sixth length is greater than the fifth length.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 23, 2017
    Inventors: Shih-Ming Chang, Chih-Tsung Shih
  • Patent number: 9576099
    Abstract: Provided is a method of fabricating a semiconductor device. An integrated circuit (IC) layout plan is obtained. The IC layout plan contains critical features and non-critical features. Locational information regarding a defect on a blank reticle is obtained. The blank reticle is a candidate reticle for being patterned with the IC layout plan. Based on the locational information regarding the defect and the IC layout plan, a determination is made that at some of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan, regardless of whether the IC layout plan is globally manipulated or not before being patterned onto the blank reticle. In response to the determination, selected local portions of the IC layout plan are re-arranged such that none of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Chia-Hao Yu
  • Patent number: 9564327
    Abstract: One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed.
    Type: Grant
    Filed: May 25, 2015
    Date of Patent: February 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai, Ken-Hsien Hsieh, Ru-Gun Liu
  • Patent number: 9541846
    Abstract: A system and method is provided for providing a thermal distribution on a workpiece during a lithographic process. The system provides a source of lithographic energy to workpiece, such as a workpiece having a lithographic film formed thereover. A workpiece support having a plurality of thermal devices embedded therein is configured to support the workpiece concurrent to an exposure of the workpiece to the lithographic energy. A controller individually controls a temperature of each of the plurality of thermal devices, therein controlling a specified temperature distribution across the workpiece associated with the exposure of the workpiece to the lithographic energy. Controlling the temperature of the thermal devices can be based on a model, a measured temperature of the workpiece, and/or a prediction of a temperature at one or more locations on the workpiece.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Ming Chang