Abstract: The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Abstract: The present disclosure provides a method that includes forming a first pattern feature and a second pattern feature over a material layer by a first photolithographic process. The method also includes forming a first spacer feature on a sidewall of the first pattern feature and a second spacer feature on a sidewall of the second pattern feature. Additionally, the method includes forming a third pattern feature on the material layer between the first spacer feature and the second spacer feature by a second photolithographic process. In addition, the method includes removing the first and second spacer features to expose a portion of the material layer.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

Abstract: An inverse animal feeder comprises a feeding device, a power controlling device and a tray. The feeding device comprises a cover plate and a feeding opening inside the cover plate. The power controlling device comprises a motor in a main frame, a power source and a controller for feeding automatically. The tray mounted below the power controlling device and in an outer frame, and the tray is driven by the motor. The outer frame has a plurality of through holes; the main frame is mounted between the cover plate and the outer frame; and the cover plate is connected to the main frame by holders. Additionally, the main frame has at least one fastening block and the outer frame has at least one fastening groove, so that the fastening groove is fastened to the fastening groove to connect the main frame and the outer frame.

Abstract: A system and method is provided for providing a thermal distribution on a workpiece during a lithographic process. The system provides a source of lithographic energy to workpiece, such as a workpiece having a lithographic film formed thereover. A workpiece support having a plurality of thermal devices embedded therein is configured to support the workpiece concurrent to an exposure of the workpiece to the lithographic energy. A controller individually controls a temperature of each of the plurality of thermal devices, therein controlling a specified temperature distribution across the workpiece associated with the exposure of the workpiece to the lithographic energy. Controlling the temperature of the thermal devices can be based on a model, a measured temperature of the workpiece, and/or a prediction of a temperature at one or more locations on the workpiece.

Abstract: A method for forming a photomask is provided. The method includes forming a light blocking layer over a transparent substrate. The method includes forming a mask layer over the light blocking layer. The mask layer covers a first portion of the light blocking layer, and the first portion is over a second portion of the transparent substrate. The method includes removing the light blocking layer, which is not covered by the mask layer. The method includes removing the mask layer. The first portion of the light blocking layer is removed during removing the mask layer. The method includes removing the second portion of the transparent substrate to form a first recess in the transparent substrate. The method includes forming a first light blocking structure in the first recess.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming first spacers over inner walls of the trench. The method includes removing a portion of the first spacers. The method includes forming a filling layer into the trench to cover the first spacers. The filling layer and the first spacers together form a strip structure. The method includes removing the first layer. The method includes forming second spacers over two opposite first sidewalls of the strip structure. The method includes forming third spacers over second sidewalls of the second spacers. The method includes removing the filling layer and the second spacers.

Abstract: Various examples of a technique for performing optical proximity correction and for forming a photomask are provided herein. In some examples, a layout is received that includes a shape to be formed on a photomask. A plurality of target lithographic contours are determined for the shape that includes a first target contour for a first set of process conditions and a second target contour that is different from the first target contour for a second set of process conditions. A lithographic simulation of the layout is performed to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions. A modification to the layout is determined based on edge placement errors between the first simulated contour and the first target contour and between the second simulated contour and the second target contour.

Abstract: A lithography apparatus is provided. The lithography apparatus includes an exposure system and a fluid handling system. The exposure system is configured to expose an exposure area on a substrate with an energy flow. The fluid handling system is configured to provide a heat transfer fluid flowing through a non-exposure area other than the exposure area on the substrate, to take heat away from the substrate.

Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.

Abstract: A lithography system is provided. The lithography system includes a mask and an optical module. The optical module is configured to optically form an invisible pellicle over the mask to protect the mask from contaminant particles.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first cut pattern in a first hard mask layer formed over the patterning-target layer; forming a second cut pattern in a second hard mask layer formed over the patterning layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the second cut pattern in the second hard mask layer and a portion of the patterning-target layer within a first trench; and selectively removing a portion of the first cut pattern in the first hard mask layer and a portion of the patterning-target layer within a second trench.

Abstract: Methods disclosed herein form semiconductor devices having minimum spacings that correlate with spacer widths. An exemplary method includes forming a target layer over a substrate, forming a patterning layer over the target layer, and etching the target layer using the patterning layer as an etch mask. The patterning layer includes a first pattern feature, a second pattern feature spaced a first distance (corresponding with a first width of a first spacer fabricated during a first spacer patterning process) from the first pattern feature, and a third pattern feature spaced a second distance (corresponding with a second width of a second spacer fabricated during a second spacer patterning process) from the first pattern feature and a third distance (corresponding with a third width of a third spacer formed during the second spacer patterning process) from the second pattern feature.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

Abstract: A system and method is provided for providing a thermal distribution on a workpiece during a lithographic process. The system provides a source of lithographic energy to workpiece, such as a workpiece having a lithographic film formed thereover. A workpiece support having a plurality of thermal devices embedded therein is configured to support the workpiece concurrent to an exposure of the workpiece to the lithographic energy. A controller individually controls a temperature of each of the plurality of thermal devices, therein controlling a specified temperature distribution across the workpiece associated with the exposure of the workpiece to the lithographic energy. Controlling the temperature of the thermal devices can be based on a model, a measured temperature of the workpiece, and/or a prediction of a temperature at one or more locations on the workpiece.

Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first cut pattern in a first hard mask layer formed over the patterning-target layer; forming a second cut pattern in a second hard mask layer formed over the patterning layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the second cut pattern in the second hard mask layer and a portion of the patterning-target layer within a first trench; and selectively removing a portion of the first cut pattern in the first hard mask layer and a portion of the patterning-target layer within a second trench.

Abstract: A system and method is provided for providing a thermal distribution on a workpiece during a lithographic process. The system provides a source of lithographic energy to workpiece, such as a workpiece having a lithographic film formed thereover. A workpiece support having a plurality of thermal devices embedded therein is configured to support the workpiece concurrent to an exposure of the workpiece to the lithographic energy. A controller individually controls a temperature of each of the plurality of thermal devices, therein controlling a specified temperature distribution across the workpiece associated with the exposure of the workpiece to the lithographic energy. Controlling the temperature of the thermal devices can be based on a model, a measured temperature of the workpiece, and/or a prediction of a temperature at one or more locations on the workpiece.