Patents by Inventor Shih-Ming Chen

Shih-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8154505
    Abstract: The backlight module includes a first lamp, a second lamp, a circuit board and a driving circuit board. The circuit board includes chambers to be connected to the first lamp and the second lamp, and capacitors to stabilize a voltage across two ends of each of the first lamp and the second lamp. The driving circuit board includes an inverter for driving the first lamp and the second lamp via the circuit board.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: April 10, 2012
    Assignee: Chimei Innolux Corporation
    Inventors: Wen-Tsung Lin, Tz-Lung Su, Shih-Ming Chen
  • Publication number: 20120061129
    Abstract: A circuit board structure, comprising: a first metal layer, including at least one cavity; and a plurality of first pads, for connecting at least one differential signal transmission line; wherein at least part of a vertical projection of the first pad, which is projected on the first metal layer, is overlapped with the cavity.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 15, 2012
    Inventors: Ying-Jiunn Lai, Shih-Ming Chen, Tzu-Wei Yeh
  • Publication number: 20120056295
    Abstract: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.
    Type: Application
    Filed: November 11, 2011
    Publication date: March 8, 2012
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: CHIH-PING LIN, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang
  • Patent number: 8080455
    Abstract: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: December 20, 2011
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang
  • Publication number: 20110292690
    Abstract: A multi-winding high step-up DC-DC converter includes a three-winding transformer to transform a low DC voltage to a high DC voltage; a power switch to control the energy flux of the primary winding of the three-winding transformer based on turning on/off the power switch; a first diode to control the current of the first secondary winding of the three-winding transformer; a second diode to control the current of the second secondary winding of the three-winding transformer; and a third diode to control the current of the primary winding. When the DC-DC converter is in the first operation state, the switch and the second diode are in on state, and the first and the third diodes are in off state. When the DC-DC converter is in the second operation state, the switch and the second diode are in off state, and the first and the third diodes are in on state.
    Type: Application
    Filed: April 6, 2011
    Publication date: December 1, 2011
    Applicant: National Cheng Kung University
    Inventors: Tsorng-Juu Liang, Jiann-Fuh Chen, Kuo-Ching Tseng, Shih-Ming Chen
  • Patent number: 8067283
    Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method includes providing a substrate. A first gate insulating layer and a second gate insulating layer are formed on the substrate, respectively. A gate layer is blanketly formed. A portion of the gate layer, the first gate insulating layer and the second gate insulating layer are removed to form a first gate, a remaining first gate insulating layer, a second gate and a remaining second gate insulating layer. The remaining first gate insulating layer not covered by the first gate has a first thickness, and the remaining second gate insulating layer not covered by the second gate has a second thickness, wherein a ratio between the first thickness and the second thickness is about 10 to 20. A pair of first spacers and a pair of second spacers are formed on sidewalls of the first gate and the second gate, respectively.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: November 29, 2011
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Ping Lin, Shih-Ming Chen, Hsiao-Ying Yang, Wen-Hsien Liu, Po-Sheng Hu
  • Patent number: 8063439
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: November 22, 2011
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
  • Patent number: 7965441
    Abstract: An optical film with super low retardation, including metal oxide nano-particles dispersed in a transparent resin having a three-dimensional crosslinking structure. The optical film has about 0-2 nm in-plane retardation (Ro) and almost zero out-of-plane retardation (Rth). The optical film can replace conventional triacetyl cellulose (TAC) as a polarizer protective film to improve black-white contrast and color shift on liquid crystal displays at wide viewing angles.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: June 21, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Shih-Ming Chen, Young-Jen Lee, Tzong-Ming Lee
  • Publication number: 20110117709
    Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method includes providing a substrate. A first gate insulating layer and a second gate insulating layer are formed on the substrate, respectively. A gate layer is blanketly formed. A portion of the gate layer, the first gate insulating layer and the second gate insulating layer are removed to form a first gate, a remaining first gate insulating layer, a second gate and a remaining second gate insulating layer. The remaining first gate insulating layer not covered by the first gate has a first thickness, and the remaining second gate insulating layer not covered by the second gate has a second thickness, wherein a ratio between the first thickness and the second thickness is about 10 to 20. A pair of first spacers and a pair of second spacers are formed on sidewalls of the first gate and the second gate, respectively.
    Type: Application
    Filed: November 13, 2009
    Publication date: May 19, 2011
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Ping LIN, Shih-Ming CHEN, Hsiao-Ying YANG, Wen-Hsien LIU, Po-Sheng HU
  • Patent number: 7935738
    Abstract: A transparent flexible film is provided, formed by curing a composition, comprising: about 40-75 parts by weight of a clay; about 15-45 parts by weight of a water-soluble polymer; about 1-10 parts by weight of a mono-functional acrylic oligomer of formula (I), wherein n1 is an integer 2-25, R1 is C1-10 alkyl or H, and R2 is H or CH3; and about 10-45 parts by weight of a bi-functional acrylic oligomer of formula (II), wherein n2 is an integer 3-50, R3 and R4 are H or CH3.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: May 3, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Kuang Chen, Shih-Ming Chen, Jia-Chi Huang, Young-Jen Lee, Li-Ching Wang
  • Publication number: 20110062500
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.
    Type: Application
    Filed: November 23, 2010
    Publication date: March 17, 2011
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
  • Publication number: 20110051430
    Abstract: An assembly structure for LED fixture includes a cooling body, a thermally conductive body and an LED module. The cooling body includes a cylinder, a center of which has a central hole; the thermally conductive body is arranged an opening and a plurality of sectional grooves, each of which is elastically deformed to make the thermally conductive body forcedly arranged into the central hole and thermally contacted with the cylinder; the LED module is connected by passing through the opening of the thermally conductive body and includes a seat body, an LED fixed to the seat body and a thermally conductive piece fitted onto the seat body and thermally contacted with the thermally conductive body; thereby, they are easily placed into the central hole of the cooling body with a capability to achieve effects of close combination and excellent contact between each constituent components.
    Type: Application
    Filed: August 25, 2009
    Publication date: March 3, 2011
    Inventor: Shih-Ming CHEN
  • Patent number: 7884471
    Abstract: Disclosed herein are intermediate and solder bump structures. In one embodiment, a structure comprises a primary solder column comprising primary solder material and configured to electrically contact a bonding pad on a semiconductor substrate. The structure also comprises at least one secondary solder column comprising secondary solder material in electrical contact with the primary solder column, the at least one secondary column having a height and volume less than a height and volume of the primary solder column. In such structures, the primary solder column is further configured to form a primary solder bump comprising the primary solder material and at least a portion of the secondary solder material through cohesion from the at least one secondary solder column when the intermediate structure undergoes a reflow process.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: February 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Ying Tsai, Shih-Ming Chen, Kuo-Wei Lin
  • Patent number: 7863147
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: January 4, 2011
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
  • Patent number: 7863742
    Abstract: An integrated circuit structure includes a passivation layer; a via opening in the passivation layer; a copper-containing via in the via opening; a polymer layer over the passivation layer, wherein the polymer layer comprises an aperture, and wherein the copper-containing via is exposed through the aperture; a post-passivation interconnect (PPI) line over the polymer layer, wherein the PPI line extends into the aperture and physically contacts the copper-via opening; and an under-bump metallurgy (UBM) over and electrically connected to the PPI line.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: January 4, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Mei Yu, Tjandra Winata Karta, Daniel Yang, Shih-Ming Chen, Chia-Jen Cheng
  • Patent number: 7863835
    Abstract: A display includes a backlight module having elongated lamps. At least a pair of the lamps has a first lamp and a second lamp that are electrically connected in series. The first lamp and the second lamp are spaced apart with at least a third lamp positioned between the first and second lamps.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: January 4, 2011
    Assignee: Chimei Innolux Corporation
    Inventors: Wen-Tsung Lin, Shih-Ming Chen, Ching-Liang Lin
  • Patent number: 7854522
    Abstract: The invention provides an antiglare film. A resin layer is disposed on a substrate. Micro-aggregates are distributed in an interior and over a surface of the resin layer. Each of the micro aggregates has a size of 0.1-3 ?m and is formed by aggregating aggregated nano-particles. The micro-aggregates distributing over the surface result in a surface roughness of the resin layer. The weight ratio of the resin layer to the micro-aggregates is 1:0.1-0.7.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: December 21, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Li-Ching Wang, Shih-Ming Chen, Jia-Chi Huang, Chih-Kuang Chen
  • Publication number: 20100314983
    Abstract: A light-emitting diode lamp with enhanced heat-conducting performance includes a light-emitting module, a heat sink and an elastic piece. The light-emitting module includes an insulating base, a light-emitting diode and a heat-conducting plate. The light-emitting diode is fixed to the insulating base. The heat-conducting plate partially surrounds the exterior of the insulating base to thermally contact the light-emitting diode. The heat sink is provided with a through-hole. The light-emitting module is inserted into the through-hole. The elastic piece is arranged between the heat-conducting plate and the insulating base to push the heat-conducting plate to thermally contact the heat sink. With the elastic piece propping the heat-conducting plate open, the outer surfaces of the heat-conducting plate can be tightly adhered to the inner walls of the through-hole, thereby enhancing the heat-conducting efficiency.
    Type: Application
    Filed: June 11, 2009
    Publication date: December 16, 2010
    Inventor: Shih-Ming CHEN
  • Publication number: 20100181639
    Abstract: A semiconductor device is provided. The semiconductor device comprises an epitaxial layer disposed on a semiconductor substrate, a plurality of electronic devices disposed on the epitaxial layer and a trench isolation structure disposed between the electric devices. The trench isolation structure comprises a trench in the epitaxial layer and the semiconductor substrate, an oxide liner on the sidewall and bottom of the trench, and a doped polysilicon layer filled in the trench. Moreover, a zero bias voltage can be applied to the doped polysilicon layer. The trench isolation structure can be used for isolating electronic devices having different operation voltages or high-voltage devices.
    Type: Application
    Filed: January 19, 2009
    Publication date: July 22, 2010
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Wei-Tsung Huang, Pi-Kuang Chuang, Shih-Ming Chen, Hsiao-Ying Yang
  • Publication number: 20100022218
    Abstract: An administration and service system for wireless terminal display devices comprises a digital supplier supplying digital images, digital video or digital music; an administration server including a user identity administration system, an authentication and authorization system and a digital content administration system, wherein the administration server exchanges digital data with the digital supplier and transmits the digital data; and a terminal display device, which is a digital electronic product communicating with the administration server via a wireless network and performing data transmission and identity administration. The wireless network is based on a Wi-Fi technology, and the terminal display device may be a digital photo frame. The primary objective of the present invention is to enable a user to administrate contents and transmit the contents to a wireless terminal display.
    Type: Application
    Filed: August 29, 2008
    Publication date: January 28, 2010
    Inventor: Shih-Ming Chen