Patents by Inventor Shih-Ping Hsu
Shih-Ping Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9941208Abstract: A substrate structure includes a metal substrate, a first connection layer, a second connection layer, a dielectric material layer, a metal core layer and an internal component. The first and second connection layers are disposed on a surface of the metal substrate. The metal core layer having an opening is disposed on a surface of the first connection layer. The internal component having a plurality of electrode pads is disposed on a surface of the second connection layer and in the opening of the metal core layer. The dielectric material layer is disposed on the surface of the metal substrate. The first and second connection layers, the metal core layer and the internal component are partially covered with the dielectric material layer. The metal core layer is electrically connected to one of the electrode pads via the first and second connection layers and the metal core layer.Type: GrantFiled: December 27, 2016Date of Patent: April 10, 2018Assignee: PHOENIX & CORPORATIONInventor: Shih-Ping Hsu
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Publication number: 20180082941Abstract: A substrate structure and its manufacturing method are provided. The substrate structure comprises a metal substrate, a first connection layer, a second connection layer, a dielectric material layer, a metal core layer and an internal component. The first and second connection layers are disposed on a surface of the metal substrate. The metal core layer having an opening is disposed on a surface of the first connection layer. The internal component having a plurality of electrode pads is disposed on a surface of the second connection layer and in the opening of the metal core layer. The dielectric material layer is disposed on the surface of the metal substrate. The first and second connection layers, the metal core layer and the internal component are partially covered with the dielectric material layer. The metal core layer is electrically connected to one of the electrode pads via the first and second connection layers and the metal core layer.Type: ApplicationFiled: December 27, 2016Publication date: March 22, 2018Inventor: Shih-Ping Hsu
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Patent number: 9905503Abstract: A package structure and a method of fabricating the same are provided. The method includes forming a first wiring layer on a carrier board, forming a plurality of first conductors on the first wiring layer, encapsulating the first wiring layer and the first conductors with a first insulating layer, forming a second wiring layer on the first insulating layer, forming a plurality of second conductors on the second wiring layer, encapsulating the second wiring layer and the second conductors with a second insulating layer, and forming at least one opening in the second insulating layer. The at least one opening extends to a second surface of the first insulating layer, such that at least one electronic component can be disposed in the at least one opening. With forming two insulating layers first followed by forming the at least one opening, there is no need to stack or laminate the substrate that already has an opening, and the electronic component is free of displacement due to any compression.Type: GrantFiled: December 9, 2015Date of Patent: February 27, 2018Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Shih-Ping Hsu, Chao-Chung Tseng
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Publication number: 20180047662Abstract: A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive pillars on the first circuit layer, forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer, forming, on the conductive pillars a second circuit layer that is electrically connected to the conductive pillars, forming a second insulating layer on the second surface of the first insulating layer and the second circuit layer, exposing a portion of a surface of the second circuit layer from the second insulating layer, and removing the carrier. The invention further provides the interposer substrate as described above.Type: ApplicationFiled: October 27, 2017Publication date: February 15, 2018Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Che-Wei Hsu, Shih-Ping Hsu, Chih-Wen Liu
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Patent number: 9893003Abstract: This disclosure provides a package substrate, a flip-chip package circuit, and their fabrication methods. The package substrate includes: a first wiring layer having a first dielectric material layer and a first metal wire protruding from the first dielectric material layer; a conductive pillar layer formed on the first wiring layer and including a molding compound layer, a second dielectric material layer formed on the molding compound layer, and a metal pillar connected to the first metal wire; a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the metal pillar; and a protection layer formed on the second wiring layer.Type: GrantFiled: October 22, 2014Date of Patent: February 13, 2018Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Che-Wei Hsu, Shih-Ping Hsu
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Patent number: 9831165Abstract: A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive pillars on the first circuit layer, forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer, forming on the conductive pillars a second circuit layer that is electrically connected to the conductive pillars, forming a second insulating layer on the second surface of the first insulating layer and the second circuit layer, exposing a portion of a surface of the second circuit layer from the second insulating layer, and removing the carrier. The invention further provides the interposer substrate as described above.Type: GrantFiled: November 19, 2014Date of Patent: November 28, 2017Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Che-Wei Hsu, Shih-Ping Hsu, Chih-Wen Liu
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Patent number: 9831217Abstract: This disclosure provides a package substrate fabrication method including: forming a first conductive wire and a first connecting unit on a first carrier substrate; forming a first dielectric layer on the first carrier substrate while enabling an end face of the first connecting unit to be exposed; bonding a second carrier substrate to the first dielectric layer and removing the first carrier substrate; disposing a first circuit chip and a second connecting unit on the first conductive wire; forming a second dielectric layer on the second carrier substrate while enabling the first circuit chip and the second connecting unit to be surrounded by the second dielectric layer and an end face of the second connecting unit to be exposed; forming a second conductive wire on the second dielectric layer; disposing a second circuit chip on the second conductive wire; and forming a third dielectric layer on the second carrier substrate.Type: GrantFiled: March 22, 2017Date of Patent: November 28, 2017Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Chu-Chin Hu, Shih-Ping Hsu, Che-Wei Hsu, Chin-Ming Liu, Chih-Kuai Yang
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Publication number: 20170338174Abstract: A packaging substrate is provided, which includes: an insulating layer; a plurality of conductive bumps formed on the insulating layer, wherein each of the conductive bumps has a post body exposed from the insulating layer and a conductive pad embedded in the insulating layer, the post body being integrally formed with and less in width than the conductive pad; and a plurality of conductive posts disposed on the conductive pads and embedded in the insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps. The present disclosure further provides a method for fabricating the packaging substrate.Type: ApplicationFiled: January 10, 2017Publication date: November 23, 2017Inventors: Chu-Chin Hu, Shih-Ping Hsu, Che-Wei Hsu, Chin-Ming Liu, Chih-Kuai Yang
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Patent number: 9824964Abstract: This disclosure provides a package substrate, a package structure including the same and their fabrication methods. The package substrate comprises: a first wiring layer having a first metal wire and a first dielectric material layer surrounding the first metal wire; a conductive pillar layer formed on the first wiring layer and including a first metal pillar connected to the first metal wire and a molding compound layer surrounding the first metal pillar; a flexible material layer formed on the conductive pillar layer and including a first opening formed on the first metal pillar and exposing the first metal pillar; and a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the first metal pillar through the first opening, a second metal pillar formed on the second metal wire, and a protective layer surrounding the second metal wire and the second metal pillar.Type: GrantFiled: June 16, 2017Date of Patent: November 21, 2017Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Chun-Hsien Yu, Shih-Ping Hsu
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Publication number: 20170317031Abstract: This disclosure provides a package substrate and its fabrication method. The package substrate comprises: a first wiring layer including at least one first metal wire; a conductive connecting unit including a first connecting unit and a second connecting unit on the first wiring layer; a circuit chip having at least one connection terminal and disposed on the first connecting unit; a molding compound layer covering the wiring layer, the conductive connecting unit and the circuit chip; and a second wiring layer including at least one second metal wire and connected to the second connecting unit; wherein the first connecting unit is configured for connecting one of the at least one connection terminal with one of the at least one first metal wire.Type: ApplicationFiled: July 20, 2017Publication date: November 2, 2017Inventors: CHU-CHIN HU, SHIH-PING HSU, CHIN-MING LIU
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Publication number: 20170318683Abstract: A package apparatus comprises a first wiring layer, a first dielectric material layer, a first conductive pillar layer, a first buffer layer, a second wiring layer, and a protection layer. The first wiring layer has a first surface and a second surface opposite to the first surface. The first dielectric material layer is disposed within partial zone of the first wiring layer. The first conductive pillar layer is disposed on the second surface of the first wiring layer. The first buffer layer is disposed within partial zone of the first conductive pillar layer. The second wiring layer is disposed on the first buffer layer and one end of the first conductive pillar layer. The protection layer is disposed on the first buffer layer and the second wiring layer.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventor: SHIH-PING HSU
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Patent number: 9806012Abstract: The present invention discloses an IC Carrier of a semiconductor package and its manufacturing method. The IC Carrier of the semiconductor package includes a dielectric layer and a patterned conductor layer. The dielectric layer has at least one opening groove. The patterned conductor layer is embedded in the dielectric layer, wherein a part of the patterned conductor layer is as a conductive pillar, which has two exposed ends, and a part of the patterned conductor layer is as a conductive wire, which only has one exposed end.Type: GrantFiled: July 11, 2016Date of Patent: October 31, 2017Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Shih-Ping Hsu, Chao-Tsung Tseng
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Patent number: 9805996Abstract: A substrate structure and a manufacturing method thereof are provided. The substrate structure comprises a dielectric material layer, a conductive wiring layer, a metal core layer, and a conductive pillar layer. The conductive wiring layer is disposed on a surface of the dielectric material layer. The metal core layer having a metal part is disposed inside the dielectric material layer. The conductive pillar layer is disposed inside the dielectric material layer and between the metal core layer and the conductive wiring layer. The metal part has a first side and a second side opposite the first side. One of the first side and the second side is electrically connected to the conductive pillar layer. A width of the first side is different from a width of the second side.Type: GrantFiled: July 11, 2016Date of Patent: October 31, 2017Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Shih-Ping Hsu, Che-Wei Hsu, Chin-Ming Liu, Chih-Kuai Yang
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Publication number: 20170309557Abstract: This disclosure provides a package substrate and its fabrication method. The package substrate includes: a carrier; a first wiring layer formed on the carrier; a conductive pillar layer having a plurality of metal pillars on the first wiring layer; a molding compound layer formed on the first wiring layer, covering all the first wiring layer and the metal pillars, and exposing one end face of each metal pillar; a second wiring layer formed on the molding compound layer and the exposed end faces of the metal pillars; and a protection layer formed on the second wiring layer.Type: ApplicationFiled: July 11, 2017Publication date: October 26, 2017Inventors: Chin-Yao HSU, Shih-Ping HSU
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Publication number: 20170301652Abstract: This disclosure provides a package substrate fabrication method including: forming a first conductive wire and a first connecting unit on a first carrier substrate; forming a first dielectric layer on the first carrier substrate while enabling an end face of the first connecting unit to be exposed; bonding a second carrier substrate to the first dielectric layer and removing the first carrier substrate; disposing a first circuit chip and a second connecting unit on the first conductive wire; forming a second dielectric layer on the second carrier substrate while enabling the first circuit chip and the second connecting unit to be surrounded by the second dielectric layer and an end face of the second connecting unit to be exposed; forming a second conductive wire on the second dielectric layer; disposing a second circuit chip on the second conductive wire; and forming a third dielectric layer on the second carrier substrate.Type: ApplicationFiled: March 22, 2017Publication date: October 19, 2017Inventors: CHU-CHIN HU, SHIH-PING HSU, CHE-WEI HSU, CHIN-MING LIU, CHIH-KUAI YANG
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Publication number: 20170287815Abstract: This disclosure provides a package substrate, a package structure including the same and their fabrication methods. The package substrate comprises: a first wiring layer having a first metal wire and a first dielectric material layer surrounding the first metal wire; a conductive pillar layer formed on the first wiring layer and including a first metal pillar connected to the first metal wire and a molding compound layer surrounding the first metal pillar; a flexible material layer formed on the conductive pillar layer and including a first opening formed on the first metal pillar and exposing the first metal pillar; and a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the first metal pillar through the first opening, a second metal pillar formed on the second metal wire, and a protective layer surrounding the second metal wire and the second metal pillar.Type: ApplicationFiled: June 16, 2017Publication date: October 5, 2017Inventors: CHUN-HSIEN YU, SHIH-PING HSU
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Patent number: 9754982Abstract: A substrate structure is provided, including a first insulating layer, a first circuit layer embedded in and bonded to the first insulating layer; a plurality of first conductive posts formed in the first insulating layer and electrically connected to the first circuit layer, a second circuit layer formed on the first insulating layer and electrically connected to the first circuit layer through the first conductive posts, a plurality of second conductive posts and a plurality of conductive bumps formed on the second circuit layer, and a second insulating layer formed on the first insulating layer and encapsulating the second circuit layer, the second conductive posts and the conductive bumps. The second insulating layer has a cavity exposing the conductive bumps. When the substrate structure is applied to a camera lens, a sensor element can be disposed in the cavity to reduce the thickness of the overall packaging module.Type: GrantFiled: March 7, 2016Date of Patent: September 5, 2017Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Chun-Hsien Yu, Chu-Chin Hu, Shih-Ping Hsu
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Patent number: 9750142Abstract: A package apparatus comprises a first wiring layer, a first dielectric material layer, a first conductive pillar layer, a first buffer layer, a second wiring layer, and a protection layer. The first wiring layer has a first surface and a second surface opposite to the first surface. The first dielectric material layer is disposed within partial zone of the first wiring layer. The first conductive pillar layer is disposed on the second surface of the first wiring layer. The first buffer layer is disposed within partial zone of the first conductive pillar layer. The second wiring layer is disposed on the first buffer layer and one end of the first conductive pillar layer. The protection layer is disposed on the first buffer layer and the second wiring layer.Type: GrantFiled: August 13, 2014Date of Patent: August 29, 2017Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventor: Shih-Ping Hsu
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Patent number: 9741646Abstract: This disclosure provides a package substrate and its fabrication method. The package substrate includes: a carrier; a first wiring layer formed on the carrier; a conductive pillar layer having a plurality of metal pillars on the first wiring layer; a molding compound layer formed on the first wiring layer, covering all the first wiring layer and the metal pillars, and exposing one end face of each metal pillar; a second wiring layer formed on the molding compound layer and the exposed end faces of the metal pillars; and a protection layer formed on the second wiring layer.Type: GrantFiled: August 5, 2014Date of Patent: August 22, 2017Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Chin-Yao Hsu, Shih-Ping Hsu
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Patent number: 9730328Abstract: A printed circuit board with embedded component includes a double-sided printed circuit board, an electronic component, a plurality of conductive paste blocks, an insulating layer and a wiring layer near the first wiring layer, an insulating layer and a wiring layer near the second wiring layer. The double-sided printed circuit board comprising a first wiring layer, a base, and a second wiring layer. The first wiring layer and the second wiring layer are arranged on opposite sides of the base. The second wiring layer includes a plurality of electrical contact pads. The base defines a number of conductive vias. Each electrical contact pad is aligned with and electrically connected to one corresponding conductive via. The conductive paste blocks are electrically connecting to the conductive vias. The electronic component is electrically connected to the conductive paste blocks. The two insulating layers cover the electronic component and the second wiring layer.Type: GrantFiled: December 23, 2013Date of Patent: August 8, 2017Assignees: Qi Ding Technology Qinhuangdao Co., Ltd., Zhen Ding Technology Co., Ltd.Inventor: Shih-Ping Hsu