Patents by Inventor Shih-Syuan Huang
Shih-Syuan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923413Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.Type: GrantFiled: February 7, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
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Publication number: 20240047526Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate and spaced apart from each other in a first direction. The semiconductor structure further includes a gate structure wrapping around the nanostructures and a semiconductor layer attached to the nanostructures in a second direction different from the first direction. The semiconductor structure further includes inner spacers sandwiched between the semiconductor layer and the gate structure in the second direction and a silicide layer formed over the semiconductor layer. In addition, a first portion of the semiconductor layer is sandwiched between the inner spacers and the silicide layer in the second direction.Type: ApplicationFiled: October 16, 2023Publication date: February 8, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Ching CHENG, I-Sheng CHEN, Tzu-Chiang CHEN, Shih-Syuan HUANG, Hung-Li CHIANG
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Patent number: 11824088Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure further includes a first source/drain structure formed adjacent to the first nanostructures and a second source/drain structure formed adjacent to the second nanostructures. The semiconductor structure further includes a first contact plug formed over the first source/drain structure and a second contact plug formed over the second source/drain structure. In addition, a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures.Type: GrantFiled: November 22, 2021Date of Patent: November 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Ching Cheng, I-Sheng Chen, Tzu-Chiang Chen, Shih-Syuan Huang, Hung-Li Chiang
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Publication number: 20220157938Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.Type: ApplicationFiled: February 7, 2022Publication date: May 19, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ta-Chun LIN, Kuo-Hua PAN, Jhon-Jhy LIAW, Chao-Ching CHENG, Hung-Li CHIANG, Shih-Syuan HUANG, Tzu-Chiang CHEN, I-Sheng CHEN, Sai-Hooi YEONG
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Publication number: 20220085162Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure further includes a first source/drain structure formed adjacent to the first nanostructures and a second source/drain structure formed adjacent to the second nanostructures. The semiconductor structure further includes a first contact plug formed over the first source/drain structure and a second contact plug formed over the second source/drain structure. In addition, a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures.Type: ApplicationFiled: November 22, 2021Publication date: March 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Ching CHENG, I-Sheng CHEN, Tzu-Chiang CHEN, Shih-Syuan HUANG, Hung-Li CHIANG
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Patent number: 11245005Abstract: Methods for forming semiconductor structures are provided. The method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate and patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure. The method further includes forming a first trench in the first fin structure and forming a first source/drain structure in the first trench. The method further includes partially removing the first source/drain structure to form a second trench in the first source/drain structure and forming a first contact in the second trench.Type: GrantFiled: May 7, 2020Date of Patent: February 8, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
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Patent number: 11183560Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure further includes a first source/drain structure formed adjacent to the first nanostructures and a second source/drain structure formed adjacent to the second nanostructures. The semiconductor structure further includes a first contact plug formed over the first source/drain structure and a second contact plug formed over the second source/drain structure. In addition, a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures.Type: GrantFiled: November 12, 2019Date of Patent: November 23, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Ching Cheng, I-Sheng Chen, Tzu-Chiang Chen, Shih-Syuan Huang, Hung-Li Chiang
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Publication number: 20200266271Abstract: Methods for forming semiconductor structures are provided. The method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate and patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure. The method further includes forming a first trench in the first fin structure and forming a first source/drain structure in the first trench. The method further includes partially removing the first source/drain structure to form a second trench in the first source/drain structure and forming a first contact in the second trench.Type: ApplicationFiled: May 7, 2020Publication date: August 20, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ta-Chun LIN, Kuo-Hua PAN, Jhon-Jhy LIAW, Chao-Ching CHENG, Hung-Li CHIANG, Shih-Syuan HUANG, Tzu-Chiang CHEN, I-Sheng CHEN, Sai-Hooi YEONG
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Publication number: 20200083327Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure further includes a first source/drain structure formed adjacent to the first nanostructures and a second source/drain structure formed adjacent to the second nanostructures. The semiconductor structure further includes a first contact plug formed over the first source/drain structure and a second contact plug formed over the second source/drain structure. In addition, a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures.Type: ApplicationFiled: November 12, 2019Publication date: March 12, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Ching CHENG, I-Sheng CHEN, Tzu-Chiang CHEN, Shih-Syuan HUANG, Hung-Li CHIANG
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Patent number: 10522622Abstract: A multi-gate semiconductor structure includes a plurality of nanowires, a gate structure disposed over the plurality of nanowires, and source/drain structures at two ends of each of the plurality of nanowires. The source/drain structures include a conductor, and a bottom surface of the conductor is lower than the plurality of nanowires.Type: GrantFiled: May 14, 2018Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Ching Cheng, I-Sheng Chen, Tzu-Chiang Chen, Shih-Syuan Huang, Hung-Li Chiang
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Publication number: 20190348498Abstract: A multi-gate semiconductor structure includes a plurality of nanowires, a gate structure disposed over the plurality of nanowires, and source/drain structures at two ends of each of the plurality of nanowires. The source/drain structures include a conductor, and a bottom surface of the conductor is lower than the plurality of nanowires.Type: ApplicationFiled: May 14, 2018Publication date: November 14, 2019Inventors: CHAO-CHING CHENG, I-SHENG CHEN, TZU-CHIANG CHEN, SHIH-SYUAN HUANG, HUNG-LI CHIANG
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Patent number: 9899475Abstract: The present disclosure relate to an integrated chip having long-channel and short-channel transistors having channel regions with different doping profiles. In some embodiments, the integrated chip includes a first gate electrode arranged over a first channel region having first length, and a second gate electrode arranged over a second channel region having a second length greater than the first length. The first channel region and the second channel region have a dopant profile, respectively along the first length and the second length, which has a dopant concentration that is higher by edges than in a middle of the first channel region and the second channel region. The dopant concentration is also higher by the edges of the first channel region than by the edges of the second channel region.Type: GrantFiled: June 3, 2016Date of Patent: February 20, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Hsing Yu, Shih-Syuan Huang, Ken-Ichi Goto, Yi-Ming Sheu
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Patent number: 9899517Abstract: The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to a channel region. In some embodiments, the transistor device has an epitaxial source region arranged within a substrate. An epitaxial drain region is arranged within the substrate and is separated from the epitaxial source region by a channel region. A first DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial source region to a location within the epitaxial source region. A second DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial drain region to a location within the epitaxial drain region.Type: GrantFiled: November 8, 2016Date of Patent: February 20, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Hsing Yu, Shih-Syuan Huang, Yi-Ming Sheu, Ken-Ichi Goto
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Patent number: 9768297Abstract: The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure.Type: GrantFiled: November 9, 2015Date of Patent: September 19, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu, Shih-Syuan Huang, Ken-Ichi Goto, Zhiqiang Wu
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Patent number: 9659776Abstract: First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.Type: GrantFiled: May 12, 2016Date of Patent: May 23, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Kai Chen, Tsung-Hung Lee, Han-Pin Chung, Shih-Syuan Huang, Chun-Fu Cheng, Chien-Tai Chan, Kuang-Yuan Hsu, Hsien-Chin Lin, Ka-Hing Fung
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Publication number: 20170054022Abstract: The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to a channel region. In some embodiments, the transistor device has an epitaxial source region arranged within a substrate. An epitaxial drain region is arranged within the substrate and is separated from the epitaxial source region by a channel region. A first DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial source region to a location within the epitaxial source region. A second DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial drain region to a location within the epitaxial drain region.Type: ApplicationFiled: November 8, 2016Publication date: February 23, 2017Inventors: Tsung-Hsing Yu, Shih-Syuan Huang, Yi-Ming Sheu, Ken-Ichi Goto
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Patent number: 9536746Abstract: Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold voltage control for comparatively narrow transistors. In some embodiments, a semiconductor device formed on a semiconductor substrate. The semiconductor device comprises a channel comprising an epitaxial layer that forms an outgrowth above the surface of the semiconductor substrate, and a gate material formed over the epitaxial layer. In some embodiments, a method of forming a semiconductor device is disclosed. The method comprises etching the surface of a semiconductor substrate to form a recess between first and second isolation structures, forming an epitaxial layer within the recess that forms an outgrowth above the surface of the semiconductor substrate, and forming a gate material over the epitaxial layer. Other embodiments are also disclosed.Type: GrantFiled: March 13, 2014Date of Patent: January 3, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yeh Hsu, Chia-Wen Liu, Tsung-Hsing Yu, Ken-Ichi Goto, Shih-Syuan Huang
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Patent number: 9502559Abstract: The present disclosure relates to method of forming a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated device. The method forms a first dislocation stress memorization (DSM) region and a second DSM region having stressed lattices within a substrate. The substrate is selectively etched to form a source cavity and a drain cavity extending from an upper surface of the substrate to positions contacting the first DSM region and the second DSM region. An epitaxial source is formed within the source cavity and an epitaxial drain region is formed within the drain cavity. A gate structure is formed over the substrate at a location laterally between the epitaxial source region and the epitaxial drain region.Type: GrantFiled: October 12, 2015Date of Patent: November 22, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Hsing Yu, Shih-Syuan Huang, Yi-Ming Sheu, Ken-Ichi Goto
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Publication number: 20160284800Abstract: The present disclosure relate to an integrated chip having long-channel and short-channel transistors having channel regions with different doping profiles. In some embodiments, the integrated chip includes a first gate electrode arranged over a first channel region having first length, and a second gate electrode arranged over a second channel region having a second length greater than the first length. The first channel region and the second channel region have a dopant profile, respectively along the first length and the second length, which has a dopant concentration that is higher by edges than in a middle of the first channel region and the second channel region. The dopant concentration is also higher by the edges of the first channel region than by the edges of the second channel region.Type: ApplicationFiled: June 3, 2016Publication date: September 29, 2016Inventors: Tsung-Hsing Yu, Shih-Syuan Huang, Ken-Ichi Goto, Yi-Ming Sheu
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Publication number: 20160260610Abstract: First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.Type: ApplicationFiled: May 12, 2016Publication date: September 8, 2016Inventors: Hung-Kai Chen, Tsung-Hung Lee, Han-Pin Chung, Shih-Syuan Huang, Chun-Fu Cheng, Chien-Tai Chan, Kuang-Yuan Hsu, Hsien-Chin Lin, Ka-Hing Fung