Patents by Inventor Shih-Wei Peng

Shih-Wei Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11862561
    Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng
  • Patent number: 11862623
    Abstract: A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Shun-Li Chen, Kam-Tou Sio, Shih-Wei Peng, Chun-Kuang Chen, Ru-Gun Liu
  • Patent number: 11854786
    Abstract: An integrated circuit includes a plurality of first layer deep lines and a plurality of first layer shallow lines. The integrated circuit also includes a plurality of second layer deep lines and a plurality of second layer shallow lines. Each of the first layer deep lines and the first layer shallow lines is in a first conductive layer. Each of the second layer deep lines and the second layer shallow lines is in a second conductive layer above the first conductive layer.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-An Lai, Te-Hsin Chiu, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng, Chia-Tien Wu
  • Patent number: 11854974
    Abstract: One aspect of this description relates to an integrated circuit. In some aspects, the integrated circuit includes a first pattern metal layer, a second pattern metal layer disposed over the first pattern metal layer, wherein the second pattern metal layer includes a second plurality of metal tracks extending in a first direction, and a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including a first metal track segment and a second metal track segment shifted in a second direction from the first metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment and the second metal track segment are within a double cell height in the second direction.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng
  • Publication number: 20230411300
    Abstract: A method of forming an integrated circuit (IC) package includes constructing a first power distribution structure on a first die included in the IC package, thereby electrically connecting the first power distribution structure to a second power distribution structure positioned on a back side of the first die, and bonding a third power distribution structure to the first power distribution structure, the third power distribution structure being positioned on a back side of a second die.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 21, 2023
    Inventors: Shih-Wei PENG, Te-Hsin CHIU, Jiann-Tyng TZENG
  • Publication number: 20230401368
    Abstract: A method is provided, including following operations: identifying a first contact via, a second contact via, or a combination thereof in a first standard cell, wherein the first contact via is coupled between a first active region and a first conductive line on a first side, and the second contact via is coupled between a second active region and a second conductive line on a second side; calculating a first cell height according to a first width of the first and second active regions, and calculating a second cell height according to a second width of the first and second active regions; calculating multiple first available cell heights based on a ratio between the first and second cell heights; generating layout designs of multiple first cells; and manufacturing at least first one element in the integrated circuit based on the layout designs of the first cells.
    Type: Application
    Filed: May 26, 2022
    Publication date: December 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu HUANG, Wei-Cheng TZENG, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG
  • Patent number: 11842994
    Abstract: A method generating the layout diagram includes: selecting gate patterns for which a first distance from a corresponding VG pattern to a corresponding cut-gate section is equal to or greater than a first reference value; and for each of the selected gate patterns, increasing a size of the corresponding cut-gate section from a first value to a second value; the second value resulting in a first type of overhang of a corresponding remnant portion of the corresponding gate pattern; and the first type of overhang being a minimal permissible amount of overhang of the corresponding remnant portion beyond the corresponding first or second nearest active area pattern. A result is that gaps between corresponding ends of remnant portion of gate patterns are expanded.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Te-Hsin Chiu, Shih-Wei Peng, Jiann-Tyng Tzeng
  • Patent number: 11842967
    Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kam-Tou Sio, Cheng-Chi Chuang, Chia-Tien Wu, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-Cheng Lin
  • Patent number: 11842137
    Abstract: An integrated circuit includes a set of gates, a first, second and third conductive structure, and a first, second and third via. The set of gates includes a first, second and third gate. The first, second and third conductive structure extend in the first direction and are located on a second level. The first via couples the first conductive structure and the first gate. The second via couples the second conductive structure and the second gate. The third via couples the third conductive structure and the third gate. The first, second and third via are in a right angle configuration. The first and second gate are separated from each other by a first pitch. The first and third gate are separated from each other by a removed gate portion. The first and second conductive structure are separated from each other in the first direction.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Shun Li Chen, Wei-Cheng Lin
  • Publication number: 20230394216
    Abstract: A method is provided, including following operations: obtaining information on gate pitch and a ratio between the gate pitch and a first metal line pitch; comparing a preset metal line end spacing with a second metal line pitch, of multiple metal traces, and a spacing between a metal line layer and a power rail layer; in response to the comparison, defining multiple first metal line patterns overlapping multiple first gate patterns and defining multiple second metal line patterns disposed between two adjacent gate patterns in multiple second gate patterns; placing the first metal line patterns in a first row in a floorplan of an integrated circuit layout design and the second metal line patterns in a second row, adjacent the first row; and manufacturing at least one element in an integrated circuit based on the integrated circuit layout design.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei PENG, Wei-Cheng TZENG, Wei-Cheng LIN, Jiann-Tyng TZENG
  • Publication number: 20230395503
    Abstract: A method of making an integrated includes steps of etching an opening in an insulating mask to expose a first dummy contact on a backside of the integrated circuit, depositing a conductive material into the opening, the conductive material contacting a sidewall of the first dummy contact, and recessing the conductive material to expose an end of the first dummy contact. The method also includes steps of depositing an insulating material over the conductive material in the opening, removing the first dummy contact from the insulating mask to form a first contact opening, and forming a first conductive contact in the first contact opening, the first conductive contact being electrically connected to the conductive material.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 7, 2023
    Inventors: Shih-Wei PENG, Te-Hsin CHIU, Wei-An LAI, Ching-Wei TSAI, Jiann-Tyng TZENG
  • Publication number: 20230385509
    Abstract: An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 30, 2023
    Inventors: Shih-Wei Peng, Lipen Yuan, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Publication number: 20230387002
    Abstract: An integrated circuit (IC) structure includes a plurality of first metal segments in a first metal layer of a semiconductor substrate, the plurality of first metal segments corresponding to first tracks, a plurality of second metal segments in a second metal layer of the semiconductor substrate adjacent to the first metal layer, the plurality of second metal segments corresponding to second tracks perpendicular to the first tracks, and a plurality of via structures configured to electrically connect the plurality of first metal segments to the plurality of second metal segments.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Shih-Wei PENG, Chih-Min HSIAO, Ching-Hsu CHANG, Jiann-Tyng TZENG
  • Publication number: 20230387102
    Abstract: A method (of manufacturing a semiconductor device) includes generating a corresponding layout diagram including: regarding first and second active area patterns which (1) are correspondingly nearest to a boundary between, and (2) are correspondingly in, first and second abutting cells, and for each gate pattern that intersects the first or second active area pattern, selecting the gate patterns for which a first distance from a nearest corresponding via-to-gate (VG) pattern to a corresponding cut-gate section is equal to or greater than a first reference value; and for each selected gate pattern, relative to a first size, setting a size of a corresponding cut-gate section to a second size; the first size otherwise resulting in an overhang of a gate remnant portion extending towards the boundary by a first length; and the second size resulting in the overhang extending by a second length smaller than the first length.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Te-Hsin CHIU, Shih-Wei PENG, Jiann-Tyng TZENG
  • Publication number: 20230387035
    Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Kam-Tou SIO, Cheng-Chi Chuang, Chia-Tien Wu, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-Cheng Lin
  • Publication number: 20230387201
    Abstract: A method of forming a semiconductor arrangement includes forming a first source pad over a semiconductor layer. A first nanosheet is formed contacting the first source pad. A gate pad is formed adjacent the first nanosheet. A first drain pad is formed over the gate pad and contacting the first nanosheet. A backside interconnect line is formed under the gate pad and the first source pad. A first backside contact is formed contacting at least one of the backside interconnect line, the first source pad, or the gate pad.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Shih-Wei PENG, Jiann-Tyng TZENG
  • Publication number: 20230387009
    Abstract: A method for fabricating an integrated circuit includes forming a first pattern metal layer comprising a plurality of metal tracks extending in a first direction. Each of the plurality of metal tracks is separated from its adjacent one of the plurality of metal tracks by a first pitch. The method further includes forming a second pattern metal layer formed over the first pattern metal layer. The second pattern metal layer comprises a second plurality of metal tracks extending in the first direction. Each of the second plurality of metal tracks is separated from its adjacent one of the second plurality of metal tracks by a second pitch. The method further includes forming a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng
  • Publication number: 20230378288
    Abstract: A semiconductor device includes a first transistor, a second transistor, a third transistor, and a contact. The first transistor includes a first source/drain (S/D), a second S/D, and a first gate between the first S/D and the second S/D. The first transistor and the second transistor are stacked over the third transistor. The contact covers the second S/D of the first transistor. The contact is electrically connected to the second transistor and electrically isolated from the second S/D.
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Inventors: SHIH-WEI PENG, CHUN-YEN LIN, WEI-CHENG TZENG, JIANN-TYNG TZENG
  • Publication number: 20230376668
    Abstract: A method of generating an IC layout diagram includes overlapping a channel region of an upper transistor of a complementary field-effect transistor (CFET) in an IC layout with a gate region of the CFET, thereby defining a channel overlap region, positioning an isolation region in the IC layout, the isolation region including an entirety of the channel overlap region, intersecting the isolation region with a conductive region, and generating an IC layout diagram based on the IC layout.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Shih-Wei PENG, Guo-Huei WU, Wei-Cheng LIN, Hui-Zhong ZHUANG, Jiann-Tyng TZENG
  • Publication number: 20230369310
    Abstract: A semiconductor device includes a first cell. The first cell includes: a first source/drain region and a second source/drain region in a first layer; a plurality of gate electrodes in a second layer, the plurality of gate electrodes defining at least one odd-numbered track and at least one even-numbered track; a first power rail extending in a second direction perpendicular to the first direction in a third layer; a first conductive via arranged in a fourth layer, the first conductive via being within a first odd-numbered track and non-overlapped with any of the plurality of gate electrodes from a top-view perspective; a second power rail extending in the second direction in a fifth layer; and a second conductive via arranged in a sixth layer, the second conductive via being within a first even-numbered track and non-overlapped with any of the plurality of gate electrodes from a top-view perspective.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: SHIH-WEI PENG, JIANN-TYNG TZENG