Patents by Inventor Shih-Yang Sun

Shih-Yang Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11636902
    Abstract: A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: April 25, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Guan-Wei Wu, Jen-Chu Wu, Jen-Huo Wang, Yu-Chiang Liao, Shih-Yang Sun
  • Publication number: 20230048903
    Abstract: A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.
    Type: Application
    Filed: September 8, 2021
    Publication date: February 16, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Guan-Wei Wu, Jen-Chu Wu, Jen-Huo Wang, Yu-Chiang Liao, Shih-Yang Sun
  • Patent number: 11392164
    Abstract: A signal receiving circuit is provided. The signal receiving circuit includes a receiving circuit, an adjustment circuit and a boundary detection circuit. The receiving circuit is configured to receive an input signal. The adjustment circuit is configured to adjust the input signal. The boundary detection circuit is configured to detect a first signal having a first data pattern in the input signal and a second signal having a second data pattern in the input signal. The boundary detection circuit is further configured to detect a gap value between a first signal boundary of the first signal and a second signal boundary of the second signal to reflect a status of the adjustment circuit.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: July 19, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Sheng-Wen Chen, Shih-Yang Sun, Zhen-Hong Hung
  • Patent number: 11206157
    Abstract: A calibration method of an equalizer circuit for a memory storage device is disclosed. The calibration method includes: receiving a first signal; adjusting, by the equalizer circuit, the first signal according to a control parameter to output a second signal; generating a first sampling signal according to a first reference signal and the second signal, wherein the first sampling signal reflects data transmitted by the first signal; and generating a second sampling signal according to a second reference signal and the second signal and adjusting the control parameter according to the second sampling signal to calibrate the equalizer circuit, wherein a voltage value of the first reference signal is different from a voltage value of the second reference signal.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: December 21, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Zhen-Hong Hung, Sheng-Wen Chen, Shih-Yang Sun
  • Patent number: 11062781
    Abstract: An equalizer circuit, a memory storage device and a signal adjustment method are disclosed. The equalizer circuit is configured to receive an input signal, a reference voltage signal and a sensing clock signal and generate an error signal. The equalizer circuit is further configured to generate a first adjustment signal and a second adjustment signal according to the error signal. The equalizer circuit is further configured to update a control code from a first control code to a second control code according to at least one of the first adjustment signal and the second adjustment signal and generate an adjustment control signal according to the control code. The equalizer circuit is further configured to generate a feedback control signal according to the adjustment control signal to restore the control code from the second control code to the first control code.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 13, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Zhen-Hong Hung, Shih-Yang Sun, Sheng-Wen Chen
  • Publication number: 20210191453
    Abstract: A signal receiving circuit is provided. The signal receiving circuit includes a receiving circuit, an adjustment circuit and a boundary detection circuit. The receiving circuit is configured to receive an input signal. The adjustment circuit is configured to adjust the input signal. The boundary detection circuit is configured to detect a first signal having a first data pattern in the input signal and a second signal having a second data pattern in the input signal. The boundary detection circuit is further configured to detect a gap value between a first signal boundary of the first signal and a second signal boundary of the second signal to reflect a status of the adjustment circuit.
    Type: Application
    Filed: January 8, 2020
    Publication date: June 24, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Sheng-Wen Chen, Shih-Yang Sun, Zhen-Hong Hung
  • Patent number: 10965438
    Abstract: A signal receiving circuit, a memory storage device and a signal receiving method are provided. The signal receiving circuit includes an equalizer module, a clock and data recovery (CDR) circuit and a controller. The equalizer module is configured to receive a first signal and compensate the first signal to generate a second signal. The CDR circuit is configured to perform a phase locking on the second signal. The controller is configured to open or close a signal pattern filter of the CDR circuit according to the second signal, wherein the signal pattern filter is configured to filter a signal having a specific pattern in the second signal.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: March 30, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Yang Sun, Sheng-Wen Chen, Yen-Po Lin, Bo-Jing Lin, Po-Min Cheng