Patents by Inventor Shin Hirano

Shin Hirano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088184
    Abstract: There is provided a imaging device including: an N-type region formed for each pixel and configured to perform photoelectric conversion; an inter-pixel light-shielding wall penetrating a semiconductor substrate in a depth direction and formed between N-type regions configured to perform the photoelectric conversion, the N-type regions each being formed for each of pixels adjacent to each other; a P-type layer formed between the N-type region configured to perform the photoelectric conversion and the inter-pixel light-shielding wall; and a P-type region adjacent to the P-type layer and formed between the N-type region and an interface on a side of a light incident surface of the semiconductor substrate.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Tetsuya UCHIDA, Ryoji SUZUKI, Hisahiro ANSAI, Yoichi Ueda, Shinichi YOSHIDA, Yukari TAKEYA, Tomoyuki HIRANO, Hiroyuki MORI, Hirotoshi NOMURA, Yoshiharu KUDOH, Masashi OHURA, Shin IWABUCHI
  • Publication number: 20240064907
    Abstract: An object is to provide a circuit board that includes a built-in semiconductor device and has a configuration that prevents cracking and has excellent reliability in operation over a wide temperature range. As a solution, a circuit board (10A) has a configuration in which a first insulating substrate (1) is laminated on a second insulating substrate (2) while interposing a first adhesive layer (7a), and a semiconductor device (9) is embedded in an embedment portion (1c) formed in the first insulating substrate (1).
    Type: Application
    Filed: February 22, 2022
    Publication date: February 22, 2024
    Applicant: FICT LIMITED
    Inventors: Taiji Sakai, Kenji Iida, Norikazu Ozaki, Kenji Takano, Takashi Nakagawa, Takayuki Inaba, Tetsuro Miyagawa, Akira Yajima, Shin Hirano, Kota Aoi, Yoichi Abe, Mio Emura
  • Publication number: 20230180398
    Abstract: A circuit board includes a plurality of first insulating base materials and a plurality of second insulating base materials that are alternately laminated, a first metal layer being formed into a pattern shape on a first surface of the first insulating base material, and a second metal layer being formed into a pattern shape on a second surface of the first insulating base material. The first metal layer is formed into a trapezoidal shape that is large in diameter on a first surface side of the first insulating base material. The second metal layer is formed into a trapezoidal shape that is large in diameter on a second surface side of the first insulating base material. The first metal layers and the second metal layers are laminated in such a manner that the trapezoidal shapes are alternately oriented.
    Type: Application
    Filed: March 1, 2021
    Publication date: June 8, 2023
    Applicant: FICT LIMITED
    Inventors: Kenji Iida, Norikazu Ozaki, Taiji Sakai, Takashi Nakagawa, Kenji Takano, Takayuki Inaba, Akira Yajima, Shin Hirano, Kota Aoi, Tetsuro Miyagawa
  • Publication number: 20220322534
    Abstract: A method for manufacturing a circuit board, includes obtaining a second laminated body by laminating, in this order, an uncured second insulating substrate and a resin film on a second surface opposite to a first surface of a cured first insulating substrate of a first laminated body, and performing thermocompression bonding thereon. The first laminated body includes the first insulating substrate and a metal layer that is formed into a pattern shape on the first surface of the first insulating substrate. A third laminated body is obtained by forming a hole that reaches the metal layer, in the resin film, the second insulating substrate, and the first insulating substrate, from a resin film side of the second laminated body, filling conductive paste into the hole, and then peeling off the resin film. Thermocompression bonding is performed by stacking one third laminated body and another third laminated body.
    Type: Application
    Filed: June 3, 2020
    Publication date: October 6, 2022
    Applicant: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
    Inventors: Shin Hirano, Kenji Iida, Takashi Nakagawa, Kenji Takano
  • Patent number: 8186052
    Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; filling the through-hole with an insulating material; performing electroless plating to coat the surface of the base member, in which the through-hole has been filled with the insulating material, with an electroless-plated layer; applying photo resist on the electroless-plated layer formed on the surface of the base member; optically exposing and developing the photo resist so as to form a resist pattern coating an end face of the through-hole filled with the insulating material; etching an electrically conductive layer formed on the surface of the base member with using the resist pattern as a mask; and removing the resist pattern coating the end face of the through-hole from the base member with using the electroless-plated layer as a release layer.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: May 29, 2012
    Assignee: Fujitsu Limited
    Inventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Patent number: 8178791
    Abstract: A wiring substrate includes a core substrate having a first main surface and a mutually opposing second main surface, the second main surface having a conductive property. A first through hole penetrates a core substrate. A first conductive layer extends from the first main surface to the second main surface via the first through hole. An insulating layer is formed on the first conductive layer. A second through hole has the insulating layer as an interior wall. And a second conductive layer is formed inside the second through hole.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: May 15, 2012
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Abe, Kazumasa Saito, Shin Hirano, Kenji Iida
  • Patent number: 8151456
    Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; plating the base member so as to coat an inner face of the through-hole with a plated layer; applying photo resist on the base member; optically exposing and developing the photo resist so as to form a resist pattern, which coats at least a planar area of the through-hole; and etching an electrically conductive layer formed on the surface of the base member. The resist pattern is formed so as to separate an area of exposing the conductive layer a prescribed distance away from an edge of the through-hole, and the prescribed length is longer than a distance of etching a side face of the conductive layer in the etching step.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: April 10, 2012
    Assignee: Fujitsu Limited
    Inventors: Yasutomo Maehara, Kenji Iida, Tomoyuki Abe, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Patent number: 8153908
    Abstract: The circuit board is capable of tightly bonding a cable layer on a base member even if thermal expansion coefficients of the base member and the cable layer are significantly different. The circuit board comprises: the base member; and the cable layer being laminated on the base member with anchor patterns, which are electrically conductive layers formed on a surface of the base member.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: April 10, 2012
    Assignee: Fujitsu Limited
    Inventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Patent number: 8119925
    Abstract: The core layer of a core substrate is made of carbon fibers impregnated with resin. When the temperature of the core layer increases, the core layer suffers from an increase in the thickness because of thermal expansion of the resin. The core layer is sandwiched between the insulating layers containing glass fibers. The insulating layers serve to suppress an increase in the thickness of the core layer resulting from the thermal expansion of the core layer. Thermal stress is suppressed in the core substrate.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: February 21, 2012
    Assignee: Fujitsu Limited
    Inventors: Hideaki Yoshimura, Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Takashi Nakagawa, Shin Hirano
  • Patent number: 8119923
    Abstract: A circuit board has a low thermal expansion coefficient that suits the thermal expansion coefficient of an element to be mounted thereupon and can prevent the occurrence of delamination and cracking of a core layer when the circuit board is used in a low temperature environment. The circuit board is constructed by laminating a core layer and at least one wiring layer, where the at least one wiring layer has slightly smaller external dimensions in a planar direction than the core layer.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: February 21, 2012
    Assignee: Fujitsu Limited
    Inventors: Hideaki Yoshimura, Kenji Fukuzono, Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Takashi Nakagawa, Shin Hirano, Takashi Kanda
  • Patent number: 8110749
    Abstract: Large-sized through holes are formed in a core layer of a printed wiring board. Large-sized vias are formed in the shape of a cylinder along the inward wall surfaces of the large-sized through holes located within a specific area. A filling material fills the inner space of the large-sized via. A small-sized through hole penetrates through the corresponding filling material along the longitudinal axis of the small-sized through hole. A small-sized via is formed in the shape of a cylinder along the inward wall surface of the small-sized through hole. The filling material and the core layer are uniformly distributed within the specific area in the in-plane direction of the core substrate. This results in suppression of uneven distribution of thermal stress in the core layer in the in-plane direction of the core layer.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: February 7, 2012
    Assignee: Fujitsu Limited
    Inventors: Hideaki Yoshimura, Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano
  • Patent number: 8035037
    Abstract: The core substrate is capable of securely preventing short circuit between an electrically conductive core section and a plated through-hole section. The core substrate comprises: an electrically conductive core section having a pilot hole, through which a plated through-hole section is formed; electrically conductive layers coating the inner face of the pilot hole and a surface of the core section; a gas purging hole being formed in the conductive layer coating the surface of the core section; an insulating material filling a space between the inner face of the pilot hole and an outer circumferential face of the plated through-hole section; and cable layers being laminated on both side faces of the core section.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: October 11, 2011
    Assignee: Fujitsu Limited
    Inventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Publication number: 20090308651
    Abstract: A wiring substrate includes a core substrate having a first main surface and a mutually opposing second main surface, the second main surface having a conductive property. A first through hole penetrates a core substrate. A first conductive layer extends from the first main surface to the second main surface via the first through hole. An insulating layer is formed on the first conductive layer. A second through hole has the insulating layer as an interior wall. And a second conductive layer is formed inside the second through hole.
    Type: Application
    Filed: December 9, 2008
    Publication date: December 17, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki ABE, Kazumasa SAITO, Shin HIRANO, Kenji IlDA
  • Publication number: 20090294161
    Abstract: The core layer of a core substrate is made of carbon fibers impregnated with resin. When the temperature of the core layer increases, the core layer suffers from an increase in the thickness because of thermal expansion of the resin. The core layer is sandwiched between the insulating layers containing glass fibers. The insulating layers serve to suppress an increase in the thickness of the core layer resulting from the thermal expansion of the core layer. Thermal stress is suppressed in the core substrate.
    Type: Application
    Filed: February 20, 2009
    Publication date: December 3, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Hideaki YOSHIMURA, Kenji IIDA, Tomoyuki ABE, Yasutomo MAEHARA, Takashi NAKAGAWA, Shin HIRANO
  • Publication number: 20090294166
    Abstract: Large-sized through holes are formed in a core layer of a printed wiring board. Large-sized vias are formed in the shape of a cylinder along the inward wall surfaces of the large-sized through holes located within a specific area. A filling material fills the inner space of the large-sized via. A small-sized through hole penetrates through the corresponding filling material along the longitudinal axis of the small-sized through hole. A small-sized via is formed in the shape of a cylinder along the inward wall surface of the small-sized through hole. The filling material and the core layer are uniformly distributed within the specific area in the in-plane direction of the core substrate. This results in suppression of uneven distribution of thermal stress in the core layer in the in-plane direction of the core layer.
    Type: Application
    Filed: February 20, 2009
    Publication date: December 3, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Hideaki YOSHIMURA, Kenji IIDA, Tomoyuki ABE, Yasutomo MAEHARA, Shin HIRANO
  • Publication number: 20090095511
    Abstract: The circuit board is capable of tightly bonding a cable layer on a base member even if thermal expansion coefficients of the base member and the cable layer are significantly different. The circuit board comprises: the base member; and the cable layer being laminated on the base member with anchor patterns, which are electrically conductive layers formed on a surface of the base member.
    Type: Application
    Filed: July 15, 2008
    Publication date: April 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Kenji IIDA, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Publication number: 20090094824
    Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; filling the through-hole with an insulating material; performing electroless plating to coat the surface of the base member, in which the through-hole has been filled with the insulating material, with an electroless-plated layer; applying photo resist on the electroless-plated layer formed on the surface of the base member; optically exposing and developing the photo resist so as to form a resist pattern coating an end face of the through-hole filled with the insulating material; etching an electrically conductive layer formed on the surface of the base member with using the resist pattern as a mask; and removing the resist pattern coating the end face of the through-hole from the base member with using the electroless-plated layer as a release layer.
    Type: Application
    Filed: July 15, 2008
    Publication date: April 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Publication number: 20090094825
    Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; plating the base member so as to coat an inner face of the through-hole with a plated layer; applying photo resist on the base member; optically exposing and developing the photo resist so as to form a resist pattern, which coats at least a planar area of the through-hole; and etching an electrically conductive layer formed on the surface of the base member. The resist pattern is formed so as to separate an area of exposing the conductive layer a prescribed distance away from an edge of the through-hole, and the prescribed length is longer than a distance of etching a side face of the conductive layer in the etching step.
    Type: Application
    Filed: July 18, 2008
    Publication date: April 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Yasutomo MAEHARA, Kenji Iida, Tomoyuki Abe, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Publication number: 20090095524
    Abstract: The core substrate is capable of securely preventing short circuit between an electrically conductive core section and a plated through-hole section. The core substrate comprises: an electrically conductive core section having a pilot hole, through which a plated through-hole section is formed; electrically conductive layers coating the inner face of the pilot hole and a surface of the core section; a gas purging hole being formed in the conductive layer coating the surface of the core section; an insulating material filling a space between the inner face of the pilot hole and an outer circumferential face of the plated through-hole section; and cable layers being laminated on both side faces of the core section.
    Type: Application
    Filed: July 10, 2008
    Publication date: April 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Publication number: 20090095509
    Abstract: In the core substrate, short circuit between an electrically conductive core section and a plated through-hole section can be securely prevented and cables can be formed in a high dense state. The core substrate comprises: the electrically conductive core section having a pilot hole, through which the plated through-hole section is formed; cable layers being respectively laminated on the both side faces of the core section; a plated layer coating an inner face of the pilot hole; and an insulating material filling a space between the plated layer and an outer circumferential face of the plated through-hole section.
    Type: Application
    Filed: August 8, 2008
    Publication date: April 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Shin Hirano, Kenji Iida, Yasutomo Maehara, Tomoyuki Abe, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki