Abstract: Memory subword driver circuits with common transistors are disclosed. In some examples, a subword driver block of a memory device includes a plurality of subword drivers each having an output configured to be coupled to a word line coupled to a plurality of memory cells. The outputs of a first subword driver and a second subword driver of the plurality of subword drivers are coupled to a common transistor and a common word driver line, where the first subword driver and the second subword driver are respectively coupled to a first main word line and a second main word line. In such configuration, the first and second subword drivers are coupled in cascade connection so that, responsive to an active first main word line and an inactive common word driver line, a non-active potential is provided to the first subword driver from the second subword driver via the common transistor.

Abstract: Memory subword driver circuits with common transistors are disclosed. In some examples, a subword driver block of a memory device includes a plurality of subword drivers each having an output configured to be coupled to a word line coupled to a plurality of memory cells. The outputs of a first subword driver and a second subword driver of the plurality of subword drivers are coupled to a common transistor and a common word driver line, where the first subword driver and the second subword driver are respectively coupled to a first main word line and a second main word line. In such configuration, the first and second subword drivers are coupled in cascade connection so that, responsive to an active first main word line and an inactive common word driver line, a non-active potential is provided to the first subword driver from the second subword driver via the common transistor.

Abstract: Memory subword driver circuits with common transistors are disclosed. In some examples, a subword driver block of a memory device includes a plurality of subword drivers each having an output configured to be coupled to a word line coupled to a plurality of memory cells. The outputs of a first subword driver and a second subword driver of the plurality of subword drivers are coupled to a common transistor and a common word driver line, where the first subword driver and the second subword driver are respectively coupled to a first main word line and a second main word line. In such configuration, the first and second subword drivers are coupled in cascade connection so that, responsive to an active first main word line and an inactive common word driver line, a non-active potential is provided to the first subword driver from the second subword driver via the common transistor.

Abstract: Memory subword driver circuits with common transistors are disclosed. In some examples, a subword driver block of a memory device includes a plurality of subword drivers each having an output configured to be coupled to a word line coupled to a plurality of memory cells. The outputs of a first subword driver and a second subword driver of the plurality of subword drivers are coupled to a common transistor and a common word driver line, where the first subword driver and the second subword driver are respectively coupled to a first main word line and a second main word line. In such configuration, the first and second subword drivers are coupled in cascade connection so that, responsive to an active first main word line and an inactive common word driver line, a non-active potential is provided to the first subword driver from the second subword driver via the common transistor.

Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.

Abstract: Apparatuses and methods for compensation of sense amplifiers, for example, threshold voltage compensation, are disclosed. Prime memory sense amplifiers used for accessing prime memory and redundant memory sense amplifiers used for accessing redundant memory are concurrently compensated while determining whether a memory address is remapped from prime memory to redundant memory. Following the determination, sense amplifiers (e.g., prime memory sense amplifiers and/or redundant memory sense amplifiers) that are not used for accessing the memory corresponding to the memory address are precharged.

Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.

Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.

Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.

Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.

Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.

Abstract: Apparatuses and methods for compensation of sense amplifiers, for example, threshold voltage compensation, are disclosed. Prime memory sense amplifiers used for accessing prime memory and redundant memory sense amplifiers used for accessing redundant memory are concurrently compensated while determining whether a memory address is remapped from prime memory to redundant memory. Following the determination, sense amplifiers (e.g., prime memory sense amplifiers and/or redundant memory sense amplifiers) that are not used for accessing the memory corresponding to the memory address are precharged.

Abstract: Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.

Abstract: Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit configured to supply a gate of the first transistor with a first voltage to turn on the first transistor, and to supply the gate of the first transistor with a second voltage higher than the first voltage to strengthen a current drive capability of the first transistor.

Abstract: Memory devices may employ flip-flops with paired transistors in sense amplifying circuitry to sense charges stored in memory cells. Paired transistors may present mismatches in electrical characteristics, which may affect the sensitivity of the sense amplifying circuitry. Embodiments include systems and methods that compensate and/or mitigate mismatches in the electrical characteristics of the paired transistors. To that end, the memory devices may sense the mismatches during a compensation period and pre-compensate the read-out of data lines to improve the sensibility of the sense amplifying circuitry.

Abstract: Apparatuses and methods including anti-fuses and for reading and programming same are disclosed herein. An example apparatus may include an anti-fuse element comprising first, second, and third transistors coupled in series between first and second nodes such that the second transistor is between the first and third transistors. The second transistor is configured to be operated such that a punch-through current flows through the second transistor to indicate that the anti-fuse element has been programmed.

Abstract: Memory devices may employ flip-flops with paired transistors in sense amplifying circuitry to sense charges stored in memory cells. Paired transistors may present mismatches in electrical characteristics, which may affect the sensitivity of the sense amplifying circuitry. Embodiments include systems and methods that compensate and/or mitigate mismatches in the electrical characteristics of the paired transistors. To that end, the memory devices may sense the mismatches during a compensation period and pre-compensate the read-out of data lines to improve the sensibility of the sense amplifying circuitry.

Abstract: Memory devices may employ flip-flops with paired transistors in sense amplifying circuitry to sense charges stored in memory cells. Paired transistors may present mismatches in electrical characteristics, which may affect the sensitivity of the sense amplifying circuitry. Embodiments include systems and methods that compensate and/or mitigate mismatches in the electrical characteristics of the paired transistors. To that end, the memory devices may sense the mismatches during a compensation period and pre-compensate the read-out of data lines to improve the sensibility of the sense amplifying circuitry.

Abstract: Apparatuses and methods including anti-fuses and for reading and programming same are disclosed herein. An example apparatus may include an anti-fuse element comprising first, second, and third transistors coupled in series between first and second nodes such that the second transistor is between the first and third transistors. The second transistor is configured to be operated such that a punch-through current flows through the second transistor to indicate that the anti-fuse element has been programmed.

Abstract: Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit configured to supply a gate of the first transistor with a first voltage to turn on the first transistor, and to supply the gate of the first transistor with a second voltage higher than the first voltage to strengthen a current drive capability of the first transistor.