Patents by Inventor Shin Iwabuchi

Shin Iwabuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210021776
    Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.
    Type: Application
    Filed: April 30, 2020
    Publication date: January 21, 2021
    Inventors: Shin Iwabuchi, Makoto Motoyoshi
  • Publication number: 20200350346
    Abstract: The present technology relates to a solid-state imaging device capable of suppressing deterioration in dark characteristics, and an electronic apparatus. The device includes a photoelectric conversion section; a trench between the photoelectric conversion sections in adjacent pixels; and a PN junction region on a sidewall of the trench and including a P-type region and an N-type region, the P-type region having a protruding region. The device can include an inorganic photoelectric conversion section having a pn junction and an organic photoelectric conversion section having an organic photoelectric conversion film that are stacked in a depth direction within a same pixel; and a PN junction region on a sidewall of the inorganic photoelectric conversion section. The PN junction region can further include a first P-type region and an N-type region; and a second P-type region. The present technology can be applied to, for example, a back-illuminated CMOS image sensor.
    Type: Application
    Filed: October 26, 2018
    Publication date: November 5, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masashi OHURA, Shin IWABUCHI, Atsushi OKUYAMA
  • Patent number: 10645324
    Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 5, 2020
    Assignee: Sony Corporation
    Inventors: Shin Iwabuchi, Makoto Motoyoshi
  • Publication number: 20200111830
    Abstract: The present disclosure relates to a semiconductor device, a solid state imaging element, and an electronic apparatus in which the adverse effect due to hot carrier luminescence can be suppressed. In them, an element formation unit in which a plurality of elements are formed and an interconnection unit in which interconnections connecting elements are formed are stacked. A structure object formed between a light receiving element that receives light and performs photoelectric conversion and an active element that forms a peripheral circuit placed around the light receiving element in such a manner that the gap in the thickness direction of the element formation unit is not more than a prescribed spacing and formed of a material that inhibits the propagation of light is placed in the element formation unit. The present technology can be applied to a back-side illumination solid state imaging element, for example.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 9, 2020
    Applicant: SONY CORPORATION
    Inventors: Shoji KOBAYASHI, Shin IWABUCHI, Toshikazu SHIBAYAMA, Mamoru SUZUKI, Shunsuke MARUYAMA
  • Patent number: 10594972
    Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: March 17, 2020
    Assignee: Sony Corporation
    Inventors: Shin Iwabuchi, Makoto Motoyoshi
  • Patent number: 10529764
    Abstract: The present disclosure relates to a semiconductor device, a solid state imaging element, and an electronic apparatus in which the adverse effect due to hot carrier luminescence can be suppressed. In them, an element formation unit in which a plurality of elements are formed and an interconnection unit in which interconnections connecting elements are formed are stacked. A structure object formed between a light receiving element that receives light and performs photoelectric conversion and an active element that forms a peripheral circuit placed around the light receiving element in such a manner that the gap in the thickness direction of the element formation unit is not more than a prescribed spacing and formed of a material that inhibits the propagation of light is placed in the element formation unit. The present technology can be applied to a back-side illumination solid state imaging element, for example.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: January 7, 2020
    Assignee: Sony Corporation
    Inventors: Shoji Kobayashi, Shin Iwabuchi, Toshikazu Shibayama, Mamoru Suzuki, Shunsuke Maruyama
  • Patent number: 10453885
    Abstract: The present disclosure relates to a solid-state imaging apparatus and an electronic device capable of reducing a product yield and reliability risk. By forming a contact by forming an opening in an insulating film on a back surface of a peripheral circuit region without connecting a light-shielding metal on the peripheral circuit region to the ground (GND), the light-shielding metal is connected to a Si substrate. Furthermore, a light-shielding metal on a pixel region is connected to the ground (GND). Therefore, by disposing an isolated region (insulating region) where no metal is formed between the light-shielding metal on the pixel region and the light-shielding metal on the peripheral circuit region, the light-shielding metal on the pixel region does not cause a short circuit with the light-shielding metal on the peripheral circuit region. The present disclosure can be applied to, for example, a CMOS solid-state imaging apparatus used for an imaging apparatus such as a camera.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 22, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shin Iwabuchi, Kazuhiro Satou, Kensuke Motozono, Masatoshi Iwamoto
  • Patent number: 10129497
    Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: November 13, 2018
    Assignee: Sony Corporation
    Inventors: Shin Iwabuchi, Makoto Motoyoshi
  • Publication number: 20180247966
    Abstract: The present disclosure relates to a solid-state imaging apparatus and an electronic device capable of reducing a product yield and reliability risk. By forming a contact by forming an opening in an insulating film on a back surface of a peripheral circuit region without connecting a light-shielding metal on the peripheral circuit region to the ground (GND), the light-shielding metal is connected to a Si substrate. Furthermore, a light-shielding metal on a pixel region is connected to the ground (GND). Therefore, by disposing an isolated region (insulating region) where no metal is formed between the light-shielding metal on the pixel region and the light-shielding metal on the peripheral circuit region, the light-shielding metal on the pixel region does not cause a short circuit with the light-shielding metal on the peripheral circuit region. The present disclosure can be applied to, for example, a CMOS solid-state imaging apparatus used for an imaging apparatus such as a camera.
    Type: Application
    Filed: August 26, 2016
    Publication date: August 30, 2018
    Inventors: SHIN IWABUCHI, KAZUHIRO SATOU, KENSUKE MOTOZONO, MASATOSHI IWAMOTO
  • Patent number: 9955097
    Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: April 24, 2018
    Assignee: Sony Corporation
    Inventors: Shin Iwabuchi, Makoto Motoyoshi
  • Publication number: 20180054583
    Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.
    Type: Application
    Filed: November 1, 2017
    Publication date: February 22, 2018
    Inventors: Shin Iwabuchi, Makoto Motoyoshi
  • Publication number: 20170195602
    Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.
    Type: Application
    Filed: March 21, 2017
    Publication date: July 6, 2017
    Inventors: Shin Iwabuchi, Makoto Motoyoshi
  • Publication number: 20170187977
    Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.
    Type: Application
    Filed: March 13, 2017
    Publication date: June 29, 2017
    Inventors: Shin Iwabuchi, Makoto Motoyoshi
  • Patent number: 9673249
    Abstract: A back-illuminated type solid-state image pickup device (1041) includes read circuits (Tr1, Tr2) formed on one surface of a semiconductor substrate (1042) to read a signal from a photo-electric conversion element (PD) formed on the semiconductor substrate (1042), in which electric charges (e) generated in a photo-electric conversion region (1052c1) formed under at least one portion of the read circuits (Tr1, Tr2) are collected to an electric charge accumulation region (1052a) formed on one surface side of the semiconductor substrate (1042) of the photo-electric conversion element (PD) by electric field formed within the photo-electric conversion element (PD). Thus, the solid-state image pickup device and the camera are able to make the size of pixel become very small without lowering a saturation electric charge amount (Qs) and sensitivity.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: June 6, 2017
    Assignee: Sony Corporation
    Inventors: Shin Iwabuchi, Kazuhide Yokota, Takeshi Yanagita, Yasushi Maruyama
  • Publication number: 20160255296
    Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.
    Type: Application
    Filed: May 9, 2016
    Publication date: September 1, 2016
    Inventors: Shin Iwabuchi, Makoto Motoyoshi
  • Publication number: 20160211296
    Abstract: The present disclosure relates to a semiconductor device, a solid state imaging element, and an electronic apparatus in which the adverse effect due to hot carrier luminescence can be suppressed. In them, an element formation unit in which a plurality of elements are formed and an interconnection unit in which interconnections connecting elements are formed are stacked. A structure object formed between a light receiving element that receives light and performs photoelectric conversion and an active element that forms a peripheral circuit placed around the light receiving element in such a manner that the gap in the thickness direction of the element formation unit is not more than a prescribed spacing and formed of a material that inhibits the propagation of light is placed in the element formation unit. The present technology can be applied to a back-side illumination solid state imaging element, for example.
    Type: Application
    Filed: October 24, 2014
    Publication date: July 21, 2016
    Inventors: Shoji KOBAYASHI, Shin IWABUCHI, Toshikazu SHIBAYAMA, Mamoru SUZUKI, Shunsuke MARUYAMA
  • Patent number: 9263490
    Abstract: A solid-state imaging device includes a substrate in which a plurality of pixels including photoelectric converters are formed, a wiring layer that includes wirings in a plurality of layers formed via an interlayer insulating film in a front surface side of the substrate, a base electrode pad portion that includes a portion of the wirings formed in the wiring layer, an opening that penetrates the substrate from a rear surface side of the substrate and reaches the base electrode pad portion, and an embedded electrode pad layer that is formed so as to be embedded in the opening by electroless plating.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: February 16, 2016
    Assignee: SONY CORPORATION
    Inventors: Takeshi Yanagita, Hiroshi Ozaki, Shin Iwabuchi, Tomoharu Ogita
  • Publication number: 20160020234
    Abstract: A back-illuminated type solid-state image pickup device (1041) includes read circuits (Tr1, Tr2) formed on one surface of a semiconductor substrate (1042) to read a signal from a photo-electric conversion element (PD) formed on the semiconductor substrate (1042), in which electric charges (e) generated in a photo-electric conversion region (1052c1) formed under at least one portion of the read circuits (Tr1, Tr2) are collected to an electric charge accumulation region (1052a) formed on one surface side of the semiconductor substrate (1042) of the photo-electric conversion element (PD) by electric field formed within the photo-electric conversion element (PD). Thus, the solid-state image pickup device and the camera are able to make the size of pixel become very small without lowering a saturation electric charge amount (Qs) and sensitivity.
    Type: Application
    Filed: July 20, 2015
    Publication date: January 21, 2016
    Inventors: Shin Iwabuchi, Kazuhide Yokota, Takeshi Yanagita, Yasushi Maruyama
  • Patent number: 9159766
    Abstract: A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: October 13, 2015
    Assignee: SONY CORPORATION
    Inventor: Shin Iwabuchi
  • Patent number: 9117710
    Abstract: A back-illuminated type solid-state image pickup device (1041) includes read circuits (Tr1, Tr2) formed on one surface of a semiconductor substrate (1042) to read a signal from a photo-electric conversion element (PD) formed on the semiconductor substrate (1042), in which electric charges (e) generated in a photo-electric conversion region (1052c1) formed under at least one portion of the read circuits (Tr1, Tr2) are collected to an electric charge accumulation region (1052a) formed on one surface side of the semiconductor substrate (1042) of the photo-electric conversion element (PD) by electric field formed within the photo-electric conversion element (PD). Thus, the solid-state image pickup device and the camera are able to make the size of pixel become very small without lowering a saturation electric charge amount (Qs) and sensitivity.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: August 25, 2015
    Assignee: Sony Corporation
    Inventors: Shin Iwabuchi, Kazuhide Yokota, Takeshi Yanagita, Yasushi Maruyama