Patents by Inventor Shin-Jiun Kuang

Shin-Jiun Kuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11004955
    Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Jiun Kuang, Yi-Han Wang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Patent number: 10868175
    Abstract: Some embodiments of the present disclosure provide a method for fabricating a semiconductor structure. The method includes forming a recess in a substrate and forming an epitaxy region, comprising a multilayer structure with a substance having a first lattice constant larger than a second lattice constant of the substrate. Forming the epitaxy region further includes forming a first layer in proximity to an interface between the epitaxy region and the substrate with an average concentration of the substance from about 20 to about 32 percent by an in situ growth, and forming a second layer over the first layer, a bottom portion of the second layer having a concentration of the substance from about 27 percent to about 37 percent by an in situ growth operation.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Publication number: 20200365735
    Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Patent number: 10741688
    Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Publication number: 20200144395
    Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.
    Type: Application
    Filed: December 30, 2019
    Publication date: May 7, 2020
    Inventors: SHIN-JIUN KUANG, YI-HAN WANG, TSUNG-HSING YU, YI-MING SHEU
  • Patent number: 10522657
    Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Jiun Kuang, Yi-Han Wang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Publication number: 20190019881
    Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 17, 2019
    Inventors: SHIN-JIUN KUANG, YI-HAN WANG, TSUNG-HSING YU, YI-MING SHEU
  • Patent number: 10084063
    Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Jiun Kuang, Yi-Han Wang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Publication number: 20180166572
    Abstract: Some embodiments of the present disclosure provide a method for fabricating a semiconductor structure. The method includes forming a recess in a substrate and forming an epitaxy region, comprising a multilayer structure with a substance having a first lattice constant larger than a second lattice constant of the substrate. Forming the epitaxy region further includes forming a first layer in proximity to an interface between the epitaxy region and the substrate with an average concentration of the substance from about 20 to about 32 percent by an in situ growth, and forming a second layer over the first layer, a bottom portion of the second layer having a concentration of the substance from about 27 percent to about 37 percent by an in situ growth operation.
    Type: Application
    Filed: February 12, 2018
    Publication date: June 14, 2018
    Inventors: SHIN-JIUN KUANG, TSUNG-HSING YU, YI-MING SHEU
  • Publication number: 20180061986
    Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.
    Type: Application
    Filed: November 3, 2017
    Publication date: March 1, 2018
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Patent number: 9893183
    Abstract: Some embodiments of the present disclosure provide a semiconductor structure including a substrate and an epitaxy region partially disposed in the substrate. The epitaxy region includes a substance with a lattice constant that is larger than a lattice constant of the substrate. The concentration profile of a substance in the epitaxy region is monotonically increasing from a bottom portion of the epitaxy region to a of the epitaxy region. A first layer of the epitaxy region has a height to width ratio of about 2. The first layer is a layer positioned closest to the substrate, and the first layer has an average concentration of the substance from about 20 to about 32 percent. A second layer disposed over the first layer. The second layer has a bottom portion with a concentration of the substance from about 27 percent to about 37 percent.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Patent number: 9837533
    Abstract: Some embodiments of the present disclosure provide a semiconductor structure, including a substrate and a regrowth region. The substrate is made of a first material with a first lattice constant, and the regrowth region is made of the first material and a second material, having a lattice constant different from the first lattice constant. The regrowth region is partially positioned in the substrate. The regrowth region has a “tip depth” measured vertically from a surface of the substrate to a widest vertex of the regrowth region, and the tip depth being less than 10 nm. The regrowth region further includes a top layer substantially made of the first material, and the top layer has substantially the first lattice constant.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: December 5, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu, Chun-Yi Lee, Chia-Wen Liu
  • Patent number: 9831341
    Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Patent number: 9281372
    Abstract: The present disclosure provides a semiconductor structure includes a gate structure disposed over a substrate, wherein the gate structure includes a high-k dielectric layer and a work function structure. The high-k dielectric layer includes a base portion and a side portion, the side portion is extended from an end of the base portion, the side portion is substantially orthogonal to the base portion. The work function structure includes a first metal disposed over the high-k dielectric layer and a second metal disposed over the first metal and including a bottom portion and a sidewall portion extended from an end of the bottom portion, wherein the first metal includes different materials from the second metal, and a length of an interface between the sidewall portion and the bottom portion to a length of the bottom portion within the high-k dielectric layer is in a predetermined ratio.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: March 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu, Chun-Yi Lee
  • Publication number: 20160020297
    Abstract: The present disclosure provides a semiconductor structure includes a gate structure disposed over a substrate, wherein the gate structure includes a high-k dielectric layer and a work function structure. The high-k dielectric layer includes a base portion and a side portion, the side portion is extended from an end of the base portion, the side portion is substantially orthogonal to the base portion. The work function structure includes a first metal disposed over the high-k dielectric layer and a second metal disposed over the first metal and including a bottom portion and a sidewall portion extended from an end of the bottom portion, wherein the first metal includes different materials from the second metal, and a length of an interface between the sidewall portion and the bottom portion to a length of the bottom portion within the high-k dielectric layer is in a predetermined ratio.
    Type: Application
    Filed: July 17, 2014
    Publication date: January 21, 2016
    Inventors: SHIN-JIUN KUANG, TSUNG-HSING YU, YI-MING SHEU, CHUN-YI LEE
  • Publication number: 20160013316
    Abstract: Some embodiments of the present disclosure provide a semiconductor structure including a substrate and an epitaxy region partially disposed in the substrate. The epitaxy region includes a substance with a lattice constant that is larger than a lattice constant of the substrate. The concentration profile of a substance in the epitaxy region is monotonically increasing from a bottom portion of the epitaxy region to a of the epitaxy region. A first layer of the epitaxy region has a height to width ratio of about 2. The first layer is a layer positioned closest to the substrate, and the first layer has an average concentration of the substance from about 20 to about 32 percent. A second layer disposed over the first layer. The second layer has a bottom portion with a concentration of the substance from about 27 percent to about 37 percent.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 14, 2016
    Inventors: SHIN-JIUN KUANG, TSUNG-HSING YU, YI-MING SHEU
  • Publication number: 20160005863
    Abstract: Some embodiments of the present disclosure provide a semiconductor structure, including a substrate and a regrowth region. The substrate is made of a first material with a first lattice constant, and the regrowth region is made of the first material and a second material, having a lattice constant different from the first lattice constant. The regrowth region is partially positioned in the substrate. The regrowth region has a “tip depth” measured vertically from a surface of the substrate to a widest vertex of the regrowth region, and the tip depth being less than 10 nm. The regrowth region further includes a top layer substantially made of the first material, and the top layer has substantially the first lattice constant.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 7, 2016
    Inventors: SHIN-JIUN KUANG, TSUNG-HSING YU, YI-MING SHEU, CHUN-YI LEE, CHIA-WEN LIU
  • Publication number: 20150372142
    Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.
    Type: Application
    Filed: June 23, 2014
    Publication date: December 24, 2015
    Inventors: Shin-Jiun KUANG, Yi-Han WANG, Tsung-Hsing YU, Yi-Ming SHEU
  • Publication number: 20150364601
    Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.
    Type: Application
    Filed: June 16, 2014
    Publication date: December 17, 2015
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu