Patents by Inventor Shingo Akita

Shingo Akita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210164377
    Abstract: There is provided an exhaust gas purifying catalyst including a substrate and catalyst portions. The substrate includes an inflow-side cells, outflow-side cells, and porous partition walls, each partition wall separating the inflow-side cell from the outflow-side cell. The catalyst portion includes: (group A) first catalyst portions, each first catalyst portion being provided on a surface of the partition wall that faces the inflow-side cell on an upstream side in an exhaust gas flow direction; and (group B) second catalyst portions being provided on a surface of the partition wall that faces the outflow-side cell on a downstream side in the exhaust gas flow direction. Each catalyst portion of one of group A and group B includes at least one oxidizing catalyst layer and at least one reducing catalyst layer, and each catalyst portion of the other of group A and group B includes at least one oxidizing catalyst layer and/or at least one reducing catalyst layer.
    Type: Application
    Filed: April 17, 2019
    Publication date: June 3, 2021
    Inventors: Hiroki KURIHARA, Yusuke NAGAI, Shingo AKITA, Yoshinori ENDO, Takeshi MORI, Takayuki WATANABE, Tomoko TSUYAMA
  • Publication number: 20210164378
    Abstract: In an exhaust gas purifying catalyst according to the present invention, a substrate includes inflow-side cells, outflow-side cells, and porous partition walls, each partition wall separating the inflow-side cell from the outflow-side cell. Catalyst portions include: first catalyst portions, each first catalyst portion being provided on a surface of the partition wall that faces the inflow-side cell on an upstream side in an exhaust gas flow direction, and second catalyst portions, each second catalyst portion being provided on a surface of the partition wall that faces the outflow-side cell on a downstream side, and the exhaust gas purifying catalyst satisfies the following expressions: IB1/IA×100?60%, IB2/IA×100?60%, IC1/IA×100?3%, and IC2/IA×100?3%, where IA, IB1, IB2, IC1, and IC2 represent pore volumes, definitions of which can be found in the specification.
    Type: Application
    Filed: April 17, 2019
    Publication date: June 3, 2021
    Inventors: Hiroki KURIHARA, Yusuke NAGAI, Shingo AKITA, Yoshinori ENDO, Takeshi MORI, Takayuki WATANABE, Tomoko TSUYAMA
  • Publication number: 20210039080
    Abstract: A substrate (11) of an exhaust gas purification catalyst (10) includes inflow-side cells (21), outflow-side cells (22), and porous partition walls (23), each porous partition wall separating the cells (21, 22) from each other. A first catalyst portions (14) is provided at least on a portion of a side of the partition wall (23) that faces the inflow-side cell (21), the portion being located on an upstream side in an exhaust gas flow direction, and a second catalyst portion (15) is provided at least on a portion of a side of the partition wall that faces the outflow-side cell, the portion being located on a downstream side in the exhaust gas flow direction.
    Type: Application
    Filed: March 19, 2019
    Publication date: February 11, 2021
    Applicant: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Hiroki KURIHARA, Yu SAKURADA, Yusuke NAGAI, Yoshinori ENDO, Takeshi NABEMOTO, Shingo AKITA
  • Publication number: 20210001315
    Abstract: A substrate (11) includes an inflow-side cell (21), an outflow-side cell (22), and a porous, gas-permeable partition wall (23) that separates the inflow-side cell (21) and the outflow-side cell (22) from each other, and also includes a first catalyst portion (14) that is provided on a side of the partition wall (23) that faces the inflow-side cell (21) at least at a portion in upstream side in an exhaust gas flow direction, and a second catalyst portion (15) that is provided on a side of the partition wall that faces the outflow-side cell at least at a portion in downstream side.
    Type: Application
    Filed: March 19, 2019
    Publication date: January 7, 2021
    Inventors: Hiroki KURIHARA, Yu SAKURADA, Yusuke NAGAI, Yoshinori ENDO, Takeshi NABEMOTO, Shingo AKITA
  • Publication number: 20200269830
    Abstract: A controller for a hybrid vehicle is configured to execute a shifting assist process of increasing torque of a motor when performing power-on downshift of an automatic transmission and an upper limit assist torque setting process of setting an upper limit assist torque that is an upper limit value of a travel assist torque to be a smaller value when a maximum step number of the power-on downshift is large than when the maximum step number is small.
    Type: Application
    Filed: January 27, 2020
    Publication date: August 27, 2020
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shingo AKITA, Takahiro KONDO, Akio MURASUGI
  • Publication number: 20200026346
    Abstract: According to one embodiment, a memory system includes a memory chip and a controller coupled to the memory chip and configured to: instruct the memory chip to execute a write operation in one of a first operation mode and a second operation mode, a program voltage used in the second operation mode being determined on the basis of first information obtained in the first operation mode; manage a power consumption value of the second operation mode on the basis of the first information; and perform power throttling control on the basis of the managed power consumption value.
    Type: Application
    Filed: April 17, 2019
    Publication date: January 23, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yuusuke NOSAKA, Kouji WATANABE, Tomonori TSUHATA, Shingo AKITA
  • Patent number: 9601197
    Abstract: According to one embodiment, there is provided a memory system including a volatile memory and a controller. The volatile memory has 1st to Kth memory banks (K is a natural number equal to or larger than 2) that are kept in a power-on state and (K+1)th to Nthmemory banks (N is a natural number larger than K) whose power state is changed. The power state is the power-on state or a power-down state. The controller performs wake-up operation for the (K+1)th to Nth memory banks in parallel with access operation to the 1st to Kth memory banks. The wake-up operation changes the power state from the power-down state to the power-on state.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: March 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiro Nango, Shingo Akita
  • Publication number: 20150255149
    Abstract: According to one embodiment, there is provided a memory system including a volatile memory and a controller. The volatile memory has 1st to Kth memory banks (K is a natural number equal to or larger than 2) that are kept in a power-on state and (K+1)th to Nth. memory banks (N is a natural number larger than K) whose power state is changed. The power state is the power-on state or a power-down state. The controller performs wake-up operation for the (K+1)th to Nth memory banks in parallel with access operation to the 1st to Kth memory banks. The wake-up operation changes the power state from the power-down state to the power-on state.
    Type: Application
    Filed: September 9, 2014
    Publication date: September 10, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takahiro NANGO, Shingo Akita
  • Publication number: 20100169550
    Abstract: To provide a semiconductor memory device including a first controller that controls a first data transfer in which data are transferred from the first memory to a second memory in predetermined transfer units; a second controller that controls a second data transfer in which data are transferred from the second memory to a host device; and a control unit that outputs to the first controller a read instruction in which an address in the second memory is specified for each of the predetermined transfer units and creates a descriptor in which the addresses in the second memory are specified in order of transfer. The first controller outputs an end notification at each end of the first data transfer, and the second controller executes the second data transfer according to the specification in the descriptor after receiving the end notification.
    Type: Application
    Filed: August 26, 2009
    Publication date: July 1, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shingo Akita, Hiroshi Shimizu
  • Patent number: D335488
    Type: Grant
    Filed: December 31, 1991
    Date of Patent: May 11, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masakatsu Suzuki, Kazuhiro Ishii, Shingo Akita, Koji Hirotsune, Ichiro Arinobu