Patents by Inventor Shingo Tomohisa

Shingo Tomohisa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190252288
    Abstract: A semiconductor substrate according to the present invention includes a nitride semiconductor layer 203, an amorphous semiconductor layer 205 formed on one main surface side of the nitride semiconductor layer 203, a high-roughness layer 206 which is a semiconductor layer formed on the amorphous semiconductor layer 205 and has a surface roughness larger than the amorphous semiconductor layer 205, and a diamond layer 207 formed on the high-roughness layer 206. Damage to the nitride semiconductor layer can be reduced in forming the diamond layer on the nitride semiconductor layer and adhesion between the layers can be increased.
    Type: Application
    Filed: February 3, 2017
    Publication date: August 15, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tomohiro SHINAGAWA, Takeo FURUHATA, Shingo TOMOHISA
  • Patent number: 8378674
    Abstract: A magnetic field detection device including a magnetic body (magnetic flux guide) provided for adjusting a magnetic field to be applied to a magneto-resistance element. A shape of an on-substrate magnetic body in plan view is a tapered shape on one end portion side and a substantially funnel shape on another end portion side opposite the one end portion, the another end portion being larger in width than the one end portion, and a magneto-resistance element is disposed in front of an output-side end portion. In the on-substrate magnetic body, a contour of a tapered portion is not linear like a funnel, but has a curved shape in which a first curved portion protruding outward with a gentle curvature and a second curved portion protruding inward with a curvature similar to that of the first curved portion are continuously formed.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: February 19, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Taisuke Furukawa, Takeharu Kuroiwa, Shingo Tomohisa, Takashi Takenaga, Masakazu Taki, Hiroshi Takada, Yuji Abe
  • Publication number: 20100156405
    Abstract: A magnetic field detection device including a magnetic body (magnetic flux guide) provided for adjusting a magnetic field to be applied to a magneto-resistance element. A shape of an on-substrate magnetic body in plan view is a tapered shape on one end portion side and a substantially funnel shape on another end portion side opposite the one end portion, the another end portion being larger in width than the one end portion, and a magneto-resistance element is disposed in front of an output-side end portion. In the on-substrate magnetic body, a contour of a tapered portion is not linear like a funnel, but has a curved shape in which a first curved portion protruding outward with a gentle curvature and a second curved portion protruding inward with a curvature similar to that of the first curved portion are continuously formed.
    Type: Application
    Filed: May 27, 2008
    Publication date: June 24, 2010
    Applicant: Mitsubishi Electric Corporation
    Inventors: Taisuke Furukawa, Takeharu Kuroiwa, Shingo Tomohisa, Takashi Takenaga, Masakazu Taki, Hiroshi Takada, Yuji Abe
  • Patent number: 6898851
    Abstract: It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole (7) reaching an etching stopper film (4) is formed, annealing is carried out at 300 to 400° C. with the via hole (7) opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring (20) which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: May 31, 2005
    Assignees: Renesas Technology Corp., Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasutaka Nishioka, Junjiro Sakai, Shingo Tomohisa, Susumu Matsumoto, Fumio Iwamoto, Michinari Yamanaka
  • Publication number: 20040163246
    Abstract: It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole (7) reaching an etching stopper film (4) is formed, annealing is carried out at 300 to 400° C. with the via hole (7) opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring (20) which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate.
    Type: Application
    Filed: November 21, 2003
    Publication date: August 26, 2004
    Applicants: Renesas Technology Corp., MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yasutaka Nishioka, Junjiro Sakai, Shingo Tomohisa, Susumu Matsumoto, Fumio Iwamoto, Michinari Yamanaka
  • Publication number: 20030222349
    Abstract: A plurality of interconnection layers arranged at the same level are connected by an anti-diffusion insulating layer in a lateral direction. Interconnection layers arranged at different levels are electrically connected through a plug portion in a vertical direction. A second interlayer film is arranged only at a region directly below the interconnection layer and connects the interconnection layer with the anti-diffusion insulating layer in the vertical direction. A hollow space or an interlayer film with a low dielectric constant of at most 2.5 is located laterally adjacent to each of the plurality of interconnection layers. Thus, a semiconductor device having a multilayer interconnection structure that can improve both the strength of the interconnection layers and the transmission speed of signals, and a method of manufacturing the semiconductor device can be obtained.
    Type: Application
    Filed: October 30, 2002
    Publication date: December 4, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shingo Tomohisa, Mutsumi Tsuda, Tetsuo Fukada, Masakazu Taki, Kenji Shintani
  • Publication number: 20020088542
    Abstract: A plasma processing apparatus includes a reaction chamber for processing a workpiece with plasma which is generated by using one or more gases, a gas supplying means which pulsatively supplies the gases to the reaction chamber, and an exhaust means for exhausting the reaction chamber, wherein a gas supplying direction by said gas supplying means is arranged to correspond with an exhausting direction by said exhausting means.
    Type: Application
    Filed: February 1, 2000
    Publication date: July 11, 2002
    Inventors: Kazuyasu Nishikawa, Hiroki ootera, Masakazu Taki, Kenji Shintani, Shingo Tomohisa, Tatsuo Oomori
  • Patent number: 6273954
    Abstract: A gas supply system for supplying a gas into a reaction chamber is provided with a pulse valve, a mass flow controller and a back pressure controller. The mass flow controller includes a flow meter and a variable flow control valve, and the back pressure controller includes a pressure gauge and a pressure control valve. The pulse valve, the mass flow controller and the back pressure controller are connected to a controller so that operations thereof are controlled by this controller.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: August 14, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuyasu Nishikawa, Shingo Tomohisa
  • Publication number: 20010002581
    Abstract: A gas supply system for supplying a gas into a reaction chamber is provided with a pulse valve, a mass flow controller and a back pressure controller. The mass flow controller includes a flow meter and a variable flow control valve, and the back pressure controller includes a pressure gauge and a pressure control valve. The pulse valve, the mass flow controller and the back pressure controller are connected to a controller so that operations thereof are controlled by this controller.
    Type: Application
    Filed: February 26, 1999
    Publication date: June 7, 2001
    Inventors: KAZUYASU NISHIKAWA, SHINGO TOMOHISA