Patents by Inventor Shinichi Kohda
Shinichi Kohda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10439514Abstract: A light-receiving circuit receives light emitted by a light-emitting part and generates an energization signal that is an electric current based on intensity of the light. A hold circuit is configured to supply an electric charge of an energization signal to a high electric potential terminal and not to decrease a voltage of the high electric potential terminal in a case where a control circuit is sending an OFF signal. Furthermore, the hold circuit is configured not to supply the electric charge of the energization signal to the high electric potential terminal and to keep the voltage of the high electric potential terminal in a case where the control circuit is sending an ON signal. A comparison circuit compares a comparison signal and a reference signal, generates a bias voltage based on a result of the comparison between the comparison signal and the reference signal, and feeds back the bias voltage as a reference signal.Type: GrantFiled: February 28, 2017Date of Patent: October 8, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yoh Takano, Shinichi Kohda
-
Publication number: 20190260310Abstract: A light-receiving circuit receives light emitted by a light-emitting part and generates an energization signal that is an electric current based on intensity of the light. A hold circuit is configured to supply an electric charge of an energization signal to a high electric potential terminal and not to decrease a voltage of the high electric potential terminal in a case where a control circuit is sending an OFF signal. Furthermore, the hold circuit is configured not to supply the electric charge of the energization signal to the high electric potential terminal and to keep the voltage of the high electric potential terminal in a case where t e control circuit is sending an ON signal. A comparison circuit compares a comparison signal and a reference signal, generates a bias voltage based on a result of the comparison between the comparison signal and the reference signal, and feeds back the bias voltage as a reference signal.Type: ApplicationFiled: February 28, 2017Publication date: August 22, 2019Inventors: YOH TAKANO, SHINICHI KOHDA
-
Patent number: 10211144Abstract: This semiconductor device includes a semiconductor element mounted on a metal layer, first to third connection terminals that are provided on the semiconductor element, a first bus bar bonded to the first connection terminal, and a second bus bar bonded to the second connection terminal. The semiconductor element is bonded to the metal layer, and the first to third connection terminals are disposed on a top surface of the semiconductor element. One end of the first bus bar is bonded to the first connection terminal, another end of the first bus bar is an output unit, one end of the second bus bar is bonded to the second connection terminal, and another end of the second bus bar is bonded to the metal layer. A first surface of the semiconductor element and the second bus bar are at an identical potential.Type: GrantFiled: July 4, 2016Date of Patent: February 19, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shinichi Kohda, Junichi Kimura, Ryosuke Usui, Tomohide Ogura, Atsushi Watanabe
-
Patent number: 10050138Abstract: A nitride semiconductor device according to the present disclosure includes a substrate; a first nitride semiconductor layer which is formed on the substrate, and which has a C-plane as a main surface; a second nitride semiconductor layer which is formed on the first nitride semiconductor layer, and which has p-type conductivity; and a first opening which is formed in the second nitride semiconductor layer, and which reaches the first nitride semiconductor layer. The nitride semiconductor device further includes a third nitride semiconductor layer which is formed so as to cover the first opening in the second nitride semiconductor layer; a first electrode which is formed on the third nitride semiconductor layer so as to include a region of the first opening; and a second electrode which is formed on the rear surface of the substrate.Type: GrantFiled: July 21, 2016Date of Patent: August 14, 2018Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Daisuke Shibata, Kenichiro Tanaka, Masahiro Ishida, Shinichi Kohda
-
Publication number: 20180145020Abstract: This semiconductor device includes a semiconductor element mounted on a metal layer, first to third connection terminals that are provided on the semiconductor element, a first bus bar bonded to the first connection terminal, and a second bus bar bonded to the second connection terminal. The semiconductor element is bonded to the metal layer, and the first to third connection terminals are disposed on a top surface of the semiconductor element. One end of the first bus bar is bonded to the first connection terminal, another end of the first bus bar is an output unit, one end of the second bus bar is bonded to the second connection terminal, and another end of the second bus bar is bonded to the metal layer. A first surface of the semiconductor element and the second bus bar are at an identical potential.Type: ApplicationFiled: July 4, 2016Publication date: May 24, 2018Inventors: SHINICHI KOHDA, JUNICHI KIMURA, RYOSUKE USUI, TOMOHIDE OGURA, ATSUSHI WATANABE
-
Patent number: 9595606Abstract: A field-effect transistor includes a codoped layer made of AlxGa1-xN (0?x?1) and formed on a p-type Si substrate, a GaN layer formed on the codoped layer, and an AlGaN layer formed on the GaN layer. The codoped layer contains C and Si as impurity elements. The impurity concentration of C in the codoped layer is equal to or higher than 5×1017/cm3. The impurity concentration of Si in the codoped layer is lower than the impurity concentration of C. The impurity concentration of C in the GaN layer is equal to or lower than 1×1017/cm3. The thickness of the GaN layer is equal to or greater than 0.75 ?m.Type: GrantFiled: July 2, 2015Date of Patent: March 14, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kenichiro Tanaka, Shinichi Kohda, Masahiro Ishida, Tetsuzo Ueda
-
Publication number: 20160329421Abstract: A nitride semiconductor device according to the present disclosure includes a substrate; a first nitride semiconductor layer which is formed on the substrate, and which has a C-plane as a main surface; a second nitride semiconductor layer which is formed on the first nitride semiconductor layer, and which has p-type conductivity; and a first opening which is formed in the second nitride semiconductor layer, and which reaches the first nitride semiconductor layer. The nitride semiconductor device further includes a third nitride semiconductor layer which is formed so as to cover the first opening in the second nitride semiconductor layer; a first electrode which is formed on the third nitride semiconductor layer so as to include a region of the first opening; and a second electrode which is formed on the rear surface of the substrate.Type: ApplicationFiled: July 21, 2016Publication date: November 10, 2016Inventors: DAISUKE SHIBATA, KENICHIRO TANAKA, MASAHIRO ISHIDA, SHINICHI KOHDA
-
Publication number: 20160320244Abstract: In an electronic device, A heat spreader is adhered to a surface of the substrate on a side opposite to the lower surface of the substrate (hereinafter referred to as “upper surface”) by an adhesive sheet. The heat spreader supports a power transistor cooperatively with the substrate. The power transistor which is an electrical element and the heat spreader are adhered to each other by an adhesive sheet on an adhering surface on a side opposite to an adhering surface where the heat spreader is adhered to the substrate. A bus bar and the power transistor are adhered to each other by an adhesive sheet on an adhering surface on a side opposite to an adhering surface where the power transistor is adhered to the heat spreader. The thermistor is connected to a lead which is a conductive line, and is disposed on an upper surface side of substrate.Type: ApplicationFiled: January 15, 2015Publication date: November 3, 2016Inventors: JUNICHI KIMURA, MASAHISA NAKAGUCHI, SHINICHI KOHDA, NORIMITSU HOZUMI
-
Patent number: 9401402Abstract: An object of the present invention is to provide a nitride semiconductor device and a nitride semiconductor substrate in each of which a nitride semiconductor layer formed on a silicon substrate is improved in crystallinity to realize a decrease in on-resistance of a field-effect transistor. The nitride semiconductor device includes a silicon substrate, and a first nitride semiconductor layer formed over the silicon substrate and including a nitride semiconductor, wherein a Si <111> axial direction of the silicon substrate is different from a <0001> axial direction of the first nitride semiconductor layer.Type: GrantFiled: June 18, 2015Date of Patent: July 26, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shinichi Kohda, Masahiro Ishida
-
Publication number: 20150303293Abstract: A field-effect transistor includes a codoped layer made of AlxGa1-xN (0?x?1) and formed on a p-type Si substrate, a GaN layer formed on the codoped layer, and an AlGaN layer formed on the GaN layer. The codoped layer contains C and Si as impurity elements. The impurity concentration of C in the codoped layer is equal to or higher than 5×1017/cm3. The impurity concentration of Si in the codoped layer is lower than the impurity concentration of C. The impurity concentration of C in the GaN layer is equal to or lower than 1×1017/cm3. The thickness of the GaN layer is equal to or greater than 0.75 ?m.Type: ApplicationFiled: July 2, 2015Publication date: October 22, 2015Inventors: KENICHIRO TANAKA, SHINICHI KOHDA, MASAHIRO ISHIDA, TETSUZO UEDA
-
Publication number: 20150287791Abstract: An object of the present invention is to provide a nitride semiconductor device and a nitride semiconductor substrate in each of which a nitride semiconductor layer formed on a silicon substrate is improved in crystallinity to realize a decrease in on-resistance of a field-effect transistor. The nitride semiconductor device includes a silicon substrate, and a first nitride semiconductor layer formed over the silicon substrate and including a nitride semiconductor, wherein a Si <111> axial direction of the silicon substrate is different from a <0001> axial direction of the first nitride semiconductor layer.Type: ApplicationFiled: June 18, 2015Publication date: October 8, 2015Inventors: SHINICHI KOHDA, MASAHIRO ISHIDA
-
Publication number: 20130240901Abstract: A nitride semiconductor device includes a substrate, and a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, and a fourth nitride semiconductor layer sequentially formed on the substrate. A channel is formed in the third nitride semiconductor layer, and includes carriers accumulated near an interface between the third nitride semiconductor layer and the fourth nitride semiconductor layer. The second nitride semiconductor layer has a band gap larger than that of the third nitride semiconductor layer. The first nitride semiconductor layer has a band gap equal to or larger than that of the second nitride semiconductor layer, and has a carbon concentration higher than that of the second nitride semiconductor layer.Type: ApplicationFiled: May 6, 2013Publication date: September 19, 2013Applicant: Panasonic CorporationInventors: SHINICHI KOHDA, MASAHIRO ISHIDA, YASUHIRO YAMADA
-
Patent number: 8422527Abstract: A nitride based semiconductor device includes: an n-type cladding layer; an n-type GaN based guide layer placed on the n-type cladding layer; an active layer placed on the n-type GaN based guide layer; a p-type GaN based guide layer placed on the active layer; an electron block layer placed on the p-type GaN based guide layer; a stress relaxation layer placed on the electron block layer; and a p-type cladding layer placed on the stress relaxation layer, and the nitride based semiconductor device alleviates the stress occurred under the influence of the electron block layer, does not affect light distribution by the electron block layer, reduces threshold current, can suppress the degradation of reliability, can suppress degradation of the emitting end surface of the laser beam, can improve the far field pattern, and is long lasting, and fabrication method of the device is also provided.Type: GrantFiled: February 13, 2012Date of Patent: April 16, 2013Assignee: Rohm Co., Ltd.Inventors: Daisuke Nakagawa, Yoshinori Tanaka, Masahiro Murayama, Takao Fujimori, Shinichi Kohda
-
Patent number: 8405067Abstract: A nitride semiconductor element includes: a strain suppression layer formed on a silicon substrate via an initial layer; and an operation layer formed on the strain suppression layer. The strain suppression layer includes a first spacer layer, a second spacer layer formed on and in contact with the first spacer layer, and a superlattice layer formed on and in contact with the second spacer layer. The first spacer layer is larger in lattice constant than the second spacer layer. The superlattice layer has first layers and second layers smaller in lattice constant than the first layers stacked alternately on top of one another. The average lattice constant of the superlattice layer is smaller than the lattice constant of the first spacer layer and larger than the lattice constant of the second spacer layer.Type: GrantFiled: December 6, 2010Date of Patent: March 26, 2013Assignee: Panasonic CorporationInventors: Jun Shimizu, Shinichi Kohda, Yasuhiro Yamada, Naohide Wakita, Masahiro Ishida
-
Publication number: 20120299060Abstract: A nitride semiconductor device includes: a silicon substrate; a buffer layer formed on the silicon substrate and comprised of a nitride semiconductor; and an active layer formed on the buffer layer and comprised of a nitride semiconductor. The buffer layer includes a first layer formed in contact with the silicon substrate, and a second layer formed in contact with the first layer and the active layer. The carbon concentration at an interface between the first layer and the second layer is in the range of 1×1019 atoms/cm3 to 1×1021 atoms/cm3, both inclusive. The first layer has the highest carbon concentration in a portion in contact with the silicon substrate. The second layer has the highest carbon concentration in a portion in contact with the first layer, and has the lowest carbon concentration in a portion in contact with the active layer.Type: ApplicationFiled: August 8, 2012Publication date: November 29, 2012Applicant: Panasonic CorporationInventors: Shinichi KOHDA, Jun Shimizu
-
Patent number: 8198639Abstract: A method of manufacturing a semiconductor light emitting device employs a substrate formed by successively stacking an n-type semiconductor layered portion including an AlGaN layer, a light emitting layer containing In and a p-type semiconductor layered portion on a group III nitride semiconductor substrate having a larger lattice constant than AlGaN. This method includes the steps of selectively etching the substrate from the side of the p-type semiconductor layered portion along a cutting line to expose the AlGaN layer along the cutting line, forming a division guide groove along the cutting line on the exposed AlGaN layer, and dividing the substrate along the division guide groove.Type: GrantFiled: September 2, 2008Date of Patent: June 12, 2012Assignee: Rohm Co., Ltd.Inventor: Shinichi Kohda
-
Publication number: 20120140785Abstract: A nitride based semiconductor device includes: an n-type cladding layer; an n-type GaN based guide layer placed on the n-type cladding layer; an active layer placed on the n-type GaN based guide layer; a p-type GaN based guide layer placed on the active layer; an electron block layer placed on the p-type GaN based guide layer; a stress relaxation layer placed on the electron block layer; and a p-type cladding layer placed on the stress relaxation layer, and the nitride based semiconductor device alleviates the stress occurred under the influence of the electron block layer, does not affect light distribution by the electron block layer, reduces threshold current, can suppress the degradation of reliability, can suppress degradation of the emitting end surface of the laser beam, can improve the far field pattern, and is long lasting, and fabrication method of the device is also provided.Type: ApplicationFiled: February 13, 2012Publication date: June 7, 2012Inventors: Daisuke NAKAGAWA, Yoshinori TANAKA, Masahiro Murayama, Takao FUJIMORI, Shinichi KOHDA
-
Patent number: 8155162Abstract: A nitride semiconductor laser device is formed by growing a group III nitride semiconductor multilayer structure on a substrate. The group III nitride semiconductor multilayer structure has a laser resonator including an n-type semiconductor layer, a p-type semiconductor layer and a light emitting layer held between the n-type semiconductor layer and the p-type semiconductor layer. The laser resonator is arranged to be offset from the center with respect to a device width direction orthogonal to a resonator direction toward one side edge of the device. A wire bonding region having a width of not less than twice the diameter of an electrode wire to be bonded to the device is formed between the laser resonator and the other side edge of the device.Type: GrantFiled: December 30, 2010Date of Patent: April 10, 2012Assignee: Rohm Co., Ltd.Inventors: Shinichi Kohda, Yuji Ishida
-
Patent number: 8144743Abstract: A nitride based semiconductor device includes: an n-type cladding layer; an n-type GaN based guide layer placed on the n-type cladding layer; an active layer placed on the n-type GaN based guide layer; a p-type GaN based guide layer placed on the active layer; an electron block layer placed on the p-type GaN based guide layer; a stress relaxation layer placed on the electron block layer; and a p-type cladding layer placed on the stress relaxation layer, and the nitride based semiconductor device alleviates the stress occurred under the influence of the electron block layer, does not affect light distribution by the electron block layer, reduces threshold current, can suppress the degradation of reliability, can suppress degradation of the emitting end surface of the laser beam, can improve the far field pattern, and is long lasting, and fabrication method of the device is also provided.Type: GrantFiled: March 4, 2009Date of Patent: March 27, 2012Assignee: Rohm Co., Ltd.Inventors: Daisuke Nakagawa, Yoshinori Tanaka, Masahiro Murayama, Takao Fujimori, Shinichi Kohda
-
Publication number: 20110248241Abstract: A nitride semiconductor element includes: a strain suppression layer formed on a silicon substrate via an initial layer; and an operation layer formed on the strain suppression layer. The strain suppression layer includes a first spacer layer, a second spacer layer formed on and in contact with the first spacer layer, and a superlattice layer formed on and in contact with the second spacer layer. The first spacer layer is larger in lattice constant than the second spacer layer. The superlattice layer has first layers and second layers smaller in lattice constant than the first layers stacked alternately on top of one another. The average lattice constant of the superlattice layer is smaller than the lattice constant of the first spacer layer and larger than the lattice constant of the second spacer layer.Type: ApplicationFiled: December 6, 2010Publication date: October 13, 2011Inventors: Jun Shimizu, Shinichi Kohda, Yasuhiro Yamada, Naohide Wakita, Masahiro Ishida