Patents by Inventor Shinichi Uchida
Shinichi Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170186689Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Inventors: Takatsugu NEMOTO, Yasutaka NAKASHIBA, Takasuke HASHIMOTO, Shinichi UCHIDA, Kazunori GO, Hiroshi OE, Noriko YOSHIKAWA
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Publication number: 20170148751Abstract: A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.Type: ApplicationFiled: February 3, 2017Publication date: May 25, 2017Inventors: Shinpei WATANABE, Shinichi Uchida, Tadashi Maeda, Kazuo Henmi
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Patent number: 9632119Abstract: A sensor device includes a printed circuit board, a power line, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first inductor, and the second semiconductor device includes a second inductor. Each inductor is formed using an interconnect layer. The power line extends between the two inductors without overlapping the first and second inductor, when viewed from a direction perpendicular to a main surface of the printed circuit board.Type: GrantFiled: September 3, 2014Date of Patent: April 25, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takatsugu Nemoto, Yasutaka Nakashiba, Takasuke Hashimoto, Shinichi Uchida, Kazunori Go, Hiroshi Oe, Noriko Yoshikawa
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Patent number: 9589887Abstract: Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer.Type: GrantFiled: September 23, 2015Date of Patent: March 7, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinpei Watanabe, Shinichi Uchida, Tadashi Maeda, Kazuo Henmi
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Publication number: 20170043039Abstract: The problem is to provide a method that can quickly and efficiently evaluate the toxicity of human cerebrospinal fluid (CSF) with small amounts of human CSF. The problem is solved by a method comprising administering human CSF into the cerebral ventricle of a rodent such as a mouse, and evaluating the cognitive function of the rodent by using a behavioral pharmacological technique.Type: ApplicationFiled: April 16, 2015Publication date: February 16, 2017Applicant: KYOWA HAKKO KIRIN CO., LTD.Inventors: Shinichi UCHIDA, Tomoyuki KANDA
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Patent number: 9560791Abstract: Provided is a method of manufacturing a heat conductive sheet with improved adhesion and heat conductivity. The method includes the steps of molding a heat conductive resin composition, which includes heat conductive fillers and a binder resin, into a predetermined shape and curing the heat conductive resin composition to obtain a molded product of the heat conductive resin composition, cutting the molded product into sheets to obtain a molded product sheet, and pressing the molded product sheet.Type: GrantFiled: June 27, 2014Date of Patent: January 31, 2017Assignee: Dexerials CorporationInventors: Keisuke Aramaki, Atsuya Yoshinari, Takuhiro Ishii, Shinichi Uchida, Masahiko Ito
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Patent number: 9558967Abstract: An improvement is achieved in the reliability of a semiconductor device by preventing a dielectric breakdown between two semiconductor chips facing each other. During the manufacturing of first and second semiconductor chips, the process of planarizing the upper surfaces of insulating films is performed. Then, the first and second semiconductor chips are stacked via an insulating sheet with the respective insulating films of the first and second semiconductor chips facing each other such that the respective coils of the first and second semiconductor chips are magnetically coupled to each other.Type: GrantFiled: October 30, 2015Date of Patent: January 31, 2017Assignee: Renesas Electronics CorporationInventors: Shinichi Uchida, Takafumi Kuramoto, Risho Koh
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Patent number: 9536804Abstract: Provided is a method of manufacturing a heat conductive sheet that itself is imparted with stickiness and has reduced heat resistance due to improved adhesion to a heat generator and a heat dissipater and that may be fixed provisionally without the need for using an adhesive agent or the like. The method includes the steps of molding a heat conductive resin composition, which includes heat conductive fillers and a binder resin, into a predetermined shape and curing the heat conductive resin composition to obtain a molded product of the heat conductive resin composition, cutting the molded product into sheets to obtain a molded product sheet, and coating an entire surface of a sheet main body (7) with an uncured component (8) of the binder resin oozing from the sheet main body (7).Type: GrantFiled: June 27, 2014Date of Patent: January 3, 2017Assignee: Dexerials CorporationInventors: Keisuke Aramaki, Atsuya Yoshinari, Takuhiro Ishii, Shinichi Uchida, Masahiko Ito
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Patent number: 9536828Abstract: On a semiconductor substrate, coils CL5 and CL6 and pads PD5, PD6, and PD7 are formed. The coil CL5 and the coil CL6 are electrically connected in series between the pad PD5 and the pad PD6, and the pad PD7 is electrically connected between the coil CL5 and the coil CL6. The coil magnetically coupled to the coil CL5 is formed just below the coil CL5, the coil magnetically coupled to the coil CL6 is formed just below the coil CL6, and they are connected in series. When a current is flowed in the coils connected in series formed just below the coils CL5 and CL6, directions of induction current flowing in the coils CL5 and CL6 are opposed to each other in the coils CL5 and CL6.Type: GrantFiled: December 19, 2012Date of Patent: January 3, 2017Assignee: Renesas Electronics CorporationInventors: Shinichi Uchida, Hirokazu Nagase, Takuo Funaya
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Patent number: 9529022Abstract: This invention provides a sensor device at reduced cost. The sensor device includes a printed circuit board, a first terminal, a second terminal, an interconnect line, and a semiconductor device. The first terminal and second terminal are provided on the printed circuit board and coupled to a power line. The second terminal is coupled to a downstream part of the power line with respect to the first terminal. The interconnect line is disposed on the printed circuit board to couple the first terminal and second terminal to each other. In other words, the interconnect line is coupled to the power line in parallel. The semiconductor device is mounted on the printed circuit board and includes an interconnect layer and an inductor formed in the interconnect layer.Type: GrantFiled: September 4, 2014Date of Patent: December 27, 2016Assignee: Renesas Electronics CorporationInventors: Takatsugu Nemoto, Yasutaka Nakashiba, Takasuke Hashimoto, Shinichi Uchida
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Patent number: 9466591Abstract: A semiconductor device includes a first semiconductor chip that includes a first main surface, a first inductor formed on the first main surface, and a first external connection terminal formed on the first main surface; a second semiconductor chip that includes a second main surface, a second inductor formed on the second main surface, a second external connection terminal formed on the second main surface; and a first insulating film that is located between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip overlap each other such that the first main surface and the second main face each other, the semiconductor device includes a facing region in which the first semiconductor chip and the second semiconductor chip overlap each other when seen in a plan view.Type: GrantFiled: January 6, 2016Date of Patent: October 11, 2016Assignee: Renesas Electronics CorporationInventors: Shinpei Watanabe, Shinichi Uchida, Tadashi Maeda, Shigeru Tanaka
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Patent number: 9437521Abstract: A thermally conductive sheet, comprising a curable resin composition, thermally conductive fibers, and thermally conductive particles, wherein the thermally conductive sheet has a compressibility of 40% or more.Type: GrantFiled: January 6, 2016Date of Patent: September 6, 2016Assignee: DEXERIALS CORPORATIONInventors: Keisuke Aramaki, Takuhiro Ishii, Masahiko Ito, Shinichi Uchida, Atsuya Yoshinari, Syunsuke Uchida
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Publication number: 20160197066Abstract: An improvement is achieved in the reliability of a semiconductor device by preventing a dielectric breakdown between two semiconductor chips facing each other. During the manufacturing of first and second semiconductor chips, the process of planarizing the upper surfaces of insulating films is performed. Then, the first and second semiconductor chips are stacked via an insulating sheet with the respective insulating films of the first and second semiconductor chips facing each other such that the respective coils of the first and second semiconductor chips are magnetically coupled to each other.Type: ApplicationFiled: October 30, 2015Publication date: July 7, 2016Inventors: Shinichi Uchida, Takafumi Kuramoto, Risho Koh
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Publication number: 20160163660Abstract: A semiconductor device includes a semiconductor substrate, a plurality of wiring layers provided on the semiconductor substrate, a high frequency wiring provided at a first layer in the plurality of wiring layers, and a plurality of dummy metals provided in a second layer provided between the semiconductor substrate and the first layer having the high frequency wiring. The plurality of wiring layers at a top view includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region, the high frequency wiring vicinity region including a first region enclosed by an outer edge of the high frequency wiring and a second region surrounding the first region. The plurality of dummy metals are disposed dispersedly in the high frequency wiring vicinity region and in the external region respectively.Type: ApplicationFiled: February 12, 2016Publication date: June 9, 2016Inventor: SHINICHI UCHIDA
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Publication number: 20160150680Abstract: Provided is a method of manufacturing a heat conductive sheet with improved adhesion and heat conductivity. The method includes the steps of molding a heat conductive resin composition, which includes heat conductive fillers and a binder resin, into a predetermined shape and curing the heat conductive resin composition to obtain a molded product of the heat conductive resin composition, cutting the molded product into sheets to obtain a molded product sheet, and pressing the molded product sheet.Type: ApplicationFiled: June 27, 2014Publication date: May 26, 2016Applicant: Dexerials CorporationInventors: Keisuke ARAMAKI, Atsuya YOSHINARI, Takuhiro ISHII, Shinichi UCHIDA, Masahiko ITO
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Publication number: 20160141223Abstract: Provided is a method of manufacturing a heat conductive sheet that itself is imparted with stickiness and has reduced heat resistance due to improved adhesion to a heat generator and a heat dissipater and that may be fixed provisionally without the need for using an adhesive agent or the like. The method includes the steps of molding a heat conductive resin composition, which includes heat conductive fillers and a binder resin, into a predetermined shape and curing the heat conductive resin composition to obtain a molded product of the heat conductive resin composition, cutting the molded product into sheets to obtain a molded product sheet, and coating an entire surface of a sheet main body (7) with an uncured component (8) of the binder resin oozing from the sheet main body (7).Type: ApplicationFiled: June 27, 2014Publication date: May 19, 2016Applicant: Dexerials CorporationInventors: Keisuke ARAMAKI, Atsuya YOSHINARI, Takuhiro ISHII, Shinichi UCHIDA, Masahiko ITO
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Publication number: 20160118316Abstract: A thermally conductive sheet, comprising a curable resin composition, thermally conductive fibers, and thermally conductive particles, wherein the thermally conductive sheet has a compressibility of 40% or more.Type: ApplicationFiled: January 6, 2016Publication date: April 28, 2016Inventors: Keisuke Aramaki, Takuhiro Ishii, Masahiko Ito, Shinichi Uchida, Atsuya Yoshinari, Syunsuke Uchida
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Publication number: 20160118368Abstract: A semiconductor device includes a first semiconductor chip that includes a first main surface, a first inductor formed on the first main surface, and a first external connection terminal formed on the first main surface; a second semiconductor chip that includes a second main surface, a second inductor formed on the second main surface, a second external connection terminal formed on the second main surface; and a first insulating film that is located between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip overlap each other such that the first main surface and the second main face each other, the semiconductor device includes a facing region in which the first semiconductor chip and the second semiconductor chip overlap each other when seen in a plan view.Type: ApplicationFiled: January 6, 2016Publication date: April 28, 2016Inventors: Shinpei WATANABE, Shinichi UCHIDA, Tadashi MAEDA, Shigeru TANAKA
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Publication number: 20160111357Abstract: A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.Type: ApplicationFiled: December 29, 2015Publication date: April 21, 2016Applicant: Renesas Electronics CorporationInventors: Shinichi UCHIDA, Kenji NISHIKAWA, Masato KANNO, Mika YONEZAWA, Shunichi KAERIYAMA, Toshinori KIYOHARA
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Publication number: 20160093570Abstract: Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer.Type: ApplicationFiled: September 23, 2015Publication date: March 31, 2016Inventors: Shinpei WATANABE, Shinichi UCHIDA, Tadashi MAEDA, Kazuo HENMI