Abstract: A semiconductor device, includes a semiconductor device, a wiring layer provided on the semiconductor substrate, a high frequency wiring provided in the wiring layer, and plural dummy metals provided in the wiring layer apart from the high frequency wiring, wherein the wiring layer in plan view includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region, wherein the high frequency wiring vicinity region includes a first region enclosed by an outer edge of the high frequency wiring, and a second region surrounding the first region, wherein the plural dummy metals are disposed dispersedly in the high frequency wiring vicinity region and in the external region respectively, and wherein an average interval between the dummy metals in the high frequency wiring vicinity region is wider than that in the external region.

Abstract: A semiconductor device includes a substrate including a diffusion region, a device isolation region, an inductor region, and a guard ring region, a guard ring formed on the substrate to be connected to the diffusion region in the guard ring region, an insulating film formed on the substrate, in which the insulating film includes an interconnect, and an inductor formed in the inductor region, in which the guard ring region surrounds the inductor region and the device isolation region.

Abstract: A first semiconductor chip includes a first inductor and a second inductor, and a second semiconductor chip includes a third inductor and a fourth inductor. The first inductor is connected to a first receiving circuit of the first semiconductor chip, and the second inductor is connected to a second transmitting circuit of the second semiconductor chip through a first bonding wire. The third inductor is connected to a second receiving circuit of the second semiconductor chip, and the fourth inductor is connected to a first transmitting circuit of the first semiconductor chip through a second bonding wire.

Abstract: A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring.

Abstract: A semiconductor device, includes a semiconductor device, a wiring layer provided on the semiconductor substrate, a high frequency wiring provided in the wiring layer, and plural dummy metals provided in the wiring layer apart from the high frequency wiring, wherein the wiring layer in plan view includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region, wherein the high frequency wiring vicinity region includes a first region enclosed by an outer edge of the high frequency wiring, and a second region surrounding the first region, wherein the plural dummy metals are disposed dispersedly in the high frequency wiring vicinity region and in the external region respectively, and wherein an average interval between the dummy metals in the high frequency wiring vicinity region is wider than that in the external region.

Abstract: A semiconductor wafer having a plurality of interconnect layers, includes a plurality of chip-composing portions, a dicing region separating the chip-composing portions from each other, and a plurality of inter-chip interconnects formed in the dicing region and electrically connecting adjacent ones of the chip-composing portions, wherein each of the inter-chip interconnects has a width of an intermediate portion narrower than widths of connection end portions connected to the adjacent ones of the chip-composing portions.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor wafer including a plurality of interconnect layers, the semiconductor wafer including: a plurality of chip-composing portions; a dicing region separating the chip-composing portions from each other; and a plurality of inter-chip interconnects formed in the dicing region and electrically connecting adjacent ones of the chip-composing portions; and forming semiconductor chips by dicing the dicing region so as to divide the chip-composing portions, wherein each of the inter-chip interconnects has a width of an intermediate portion narrower than widths of connection end portions connected to the adjacent ones of the chip-composing portions.

Abstract: A semiconductor device, includes a semiconductor device, a wiring layer provided on the semiconductor substrate, a high frequency wiring provided in the wiring layer, and plural dummy metals provided in the wiring layer apart from the high frequency wiring, wherein the wiring layer in plan view includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region, wherein the high frequency wiring vicinity region includes a first region enclosed by an outer edge of the high frequency wiring, and a second region surrounding the first region, wherein the plural dummy metals are disposed dispersedly in the high frequency wiring vicinity region and in the external region respectively, and wherein an average interval between the dummy metals in the high frequency wiring vicinity region is wider than that in the external region.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor wafer including a plurality of interconnect layers, the semiconductor wafer including: a plurality of chip-composing portions; a dicing region separating the chip-composing portions from each other; and a plurality of inter-chip interconnects electrically connecting adjacent ones of the chip-composing portions and formed in one of the interconnect layers and in the dicing region; a dummy metal pattern comprising a plurality of dummy metals, the dummy metal pattern being formed in at least one of the interconnect layers over or below the inter-chip interconnects only in an area corresponded to a region where the inter-chip interconnects are arranged and corresponded to a region therearound; and forming semiconductor chips by dicing the dicing region so as to divide the chip-composing portions.

Abstract: A development device 4a is separated into a toner agitating portion 21 and a toner supply portion 22 by a boundary wall 23 in which a first opening 28 and a second opening 29 are formed. Inside the toner agitating portion 21, an agitation paddle 24 is rotatably supported, and inside the toner supply portion 22, components such as a development roller 25, a toner supply roller 16, and a regulation member 27 made of metal for regulating the thickness of a thin toner layer formed on the development roller 25 and for electrically charging toner are provided. A groove 27a is formed in the regulation member 27 all along the length thereof.

Abstract: A semiconductor wafer in which a plurality of regions, designed to become semiconductor chips are provided in a matrix array with interposition of a dicing line(s) respectively separating the regions. The semiconductor wafer comprises: a plurality of test pads provided in an area(s) of the semiconductor wafer disposed between the semiconductor chips, inclusive of the dicing line(s); an inter-test pad interconnect(s) provided in parallel with the test pads in the area(s) of the semiconductor wafer disposed between the regions to become semiconductor chips; the inter-test pad interconnect(s) being connected to the test pads; and an inter-chip interconnect that interconnects at least two of the regions designed to become semiconductor chips; the inter-test pad interconnect being electrically connected to the inter-chip interconnect.

Abstract: A semiconductor device includes a substrate including a diffusion region, a device isolation region, an inductor region, and a guard ring region, a guard ring formed on the substrate to be connected to the diffusion region in the guard ring region, an insulating film formed on the substrate, in which the insulating film includes an interconnect, and an inductor formed in the inductor region, in which the guard ring region surrounds the inductor region and the device isolation region.

Abstract: An image forming apparatus including a housing body in which a first end is rotatably connected with an apparatus main body, a link member in which the second end can reciprocate in a first direction, a suspended portion positioned at a restricted position when the housing body is positioned at the closed position or the intermediate open position, and positioned at a non-restricted position when the housing body is positioned at the fully open position, and a tension spring in which one end is connected to the link member and the second end is connected to the suspended portion, and when the housing body is positioned at the closed position, and the tension spring is in an extended state, when the housing body is positioned at the intermediate open position or the fully open position, and the tension spring is in a free-length state.

Abstract: Multiple transmission inductors are formed over a substrate. A signal input channel is coupled to the multiple transmission inductors and a same transmission signal is inputted to the multiple transmission inductors. A phase difference control section is provided in the signal input channel and controls a phase difference of the signal between the transmission inductors by a unit smaller than 180°.

Abstract: A semiconductor device contains a semiconductor substrate, an insulating film formed on the semiconductor substrate, an inductor formed over the semiconductor substrate while placing a portion of the insulating film in between, and a guard ring surrounding the inductor in a plan view, and isolating the inductor from other regions, wherein the guard ring contains an annular impurity diffused layer provided in the surficial portion of the semiconductor substrate, and an annular electro-conductor connected to the impurity diffused layer, and extended across a plurality of interconnect layers, up to a layer having a level of height not lower than the layer having the inductor provided therein.

Abstract: A semiconductor device, includes a semiconductor device, a wiring layer provided on the semiconductor substrate, a high frequency wiring provided in the wiring layer, and plural dummy metals provided in the wiring layer apart from the high frequency wiring, wherein the wiring layer in plan view includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region, wherein the high frequency wiring vicinity region includes a first region enclosed by an outer edge of the high frequency wiring, and a second region surrounding the first region, wherein the plural dummy metals are disposed dispersedly in the high frequency wiring vicinity region and in the external region respectively, and wherein an average interval between the dummy metals in the high frequency wiring vicinity region is wider than that in the external region.

Abstract: A semiconductor device includes, a metal wiring, which functions as an inductor or transformer, formed on a first portion of a semiconductor substrate, a plurality of first dummy layers formed in a first density on the first portion of the semiconductor substrate, a plurality of second dummy layers formed in a second density on a second portion of the semiconductor substrate, the second portion surrounding the first portion, and a plurality of third dummy layers formed in a third density higher than the first and second densities on a third portion of the semiconductor substrate, the third portion surrounding the second portion.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor wafer including a plurality of interconnect layers, the semiconductor wafer including: a plurality of chip-composing portions; a dicing region separating the chip-composing portions from each other; and a plurality of inter-chip interconnects electrically connecting adjacent ones of the chip-composing portions and formed in one of the interconnect layers and in the dicing region; a dummy metal pattern comprising a plurality of dummy metals, the dummy metal pattern being formed in at least one of the interconnect layers over or below the inter-chip interconnects only in an area corresponded to a region where the inter-chip interconnects are arranged and corresponded to a region therearound; and forming semiconductor chips by dicing the dicing region so as to divide the chip-composing portions.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor wafer including a plurality of interconnect layers, the semiconductor wafer including: a plurality of chip-composing portions; a dicing region separating the chip-composing portions from each other; and a plurality of inter-chip interconnects formed in the dicing region and electrically connecting adjacent ones of the chip-composing portions; and forming semiconductor chips by dicing the dicing region so as to divide the chip-composing portions, wherein each of the inter-chip interconnects has a width of an intermediate portion narrower than widths of connection end portions connected to the adjacent ones of the chip-composing portions.

Abstract: A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring.