Patents by Inventor Shinichi Watanuki
Shinichi Watanuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9835882Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.Type: GrantFiled: May 11, 2016Date of Patent: December 5, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki
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Publication number: 20170315312Abstract: An interposer includes a plurality of identical functional blocks arranged in the x direction, for example, and the functional blocks include a first region mounting a semiconductor chip, a second region mounting a light emitting element chip, a third region mounting a light receiving element chip, and a plurality of silicon waveguides. Then, the second and third regions are arranged between the first region and a first side along the x direction of the interposer. In addition, the plurality of silicon waveguides are arranged between the second region and the first side, and between the third region and the first side, extending from the second region toward the first side and from the third region toward the first side and are not formed between the functional blocks adjacent in the x direction.Type: ApplicationFiled: July 12, 2017Publication date: November 2, 2017Inventors: Shinichi WATANUKI, Yasutaka NAKASHIBA
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Publication number: 20170263802Abstract: A semiconductor substrate, an insulating layer made of silicon oxide formed on the semiconductor substrate and a semiconductor layer made of silicon formed on the insulating layer are provided, and the semiconductor layer constitutes an optical waveguide in an optical signal transmission line section and an optical modulator in an optical modulation section. Also, the insulating layer is removed except for a part thereof to have a hollow structure with a cavity, and both side surfaces and a lower surface of each of the semiconductor layers constituting the optical waveguide and the optical modulator are exposed and covered with air.Type: ApplicationFiled: May 26, 2017Publication date: September 14, 2017Inventors: Shinichi WATANUKI, Atsuro INADA
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Patent number: 9739964Abstract: An interposer includes a plurality of identical functional blocks arranged in the x direction, for example, and the functional blocks include a first region mounting a semiconductor chip, a second region mounting a light emitting element chip, a third region mounting a light receiving element chip, and a plurality of silicon waveguides. Then, the second and third regions are arranged between the first region and a first side along the x direction of the interposer. In addition, the plurality of silicon waveguides are arranged between the second region and the first side, and between the third region and the first side, extending from the second region toward the first side and from the third region toward the first side and are not formed between the functional blocks adjacent in the x direction.Type: GrantFiled: June 19, 2016Date of Patent: August 22, 2017Assignee: Renesas Electronics CorporationInventors: Shinichi Watanuki, Yasutaka Nakashiba
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Patent number: 9696489Abstract: A semiconductor substrate, an insulating layer made of silicon oxide formed on the semiconductor substrate and a semiconductor layer made of silicon formed on the insulating layer are provided, and the semiconductor layer constitutes an optical waveguide in an optical signal transmission line section and an optical modulator in an optical modulation section. Also, the insulating layer is removed except for a part thereof to have a hollow structure with a cavity, and both side surfaces and a lower surface of each of the semiconductor layers constituting the optical waveguide and the optical modulator are exposed and covered with air.Type: GrantFiled: March 6, 2016Date of Patent: July 4, 2017Assignee: Renesas Electronics CorporationInventors: Shinichi Watanuki, Atsuro Inada
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Publication number: 20170068047Abstract: A semiconductor device is provided with an insulating layer formed on a base substrate, an optical waveguide composed of a semiconductor layer formed on the insulating layer, and an insulating film formed along an upper surface of the insulating layer and a front surface of the optical waveguide. A peripheral edge portion of a lower surface of the optical waveguide is separated from the insulating layer, and the insulating film is buried between the peripheral edge portion and the insulating layer.Type: ApplicationFiled: August 22, 2016Publication date: March 9, 2017Inventors: TATSUYA USAMI, KEIJI SAKAMOTO, YOSHIAKI YAMAMOTO, SHINICHI WATANUKI, MASARU WAKABAYASHI, TOHRU MOGAMI, TSUYOSHI HORIKAWA, KEIZO KINOSHITA
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Publication number: 20170068051Abstract: When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.Type: ApplicationFiled: August 22, 2016Publication date: March 9, 2017Inventors: Shinichi WATANUKI, Akira MITSUIKl, Atsuro INADA, Tohru MOGAMI, Tsuyoshi HORIKAWA, Keizo KINOSHITA
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Publication number: 20170031094Abstract: A semiconductor device including an optical waveguide and a p-type semiconductor portion is configured as follows. The optical waveguide includes: a first semiconductor layer formed on an insulating layer; an insulating layer formed on the first semiconductor layer; and a second semiconductor layer formed on the insulating layer. The p-type semiconductor portion includes the first semiconductor layer. The film thickness of the p-type semiconductor portion is smaller than that of the optical waveguide. By forming the insulating layer between the first semiconductor layer and the second semiconductor layer, control of the film thicknesses of the optical waveguide and the p-type semiconductor portion is facilitated. Specifically, when the unnecessary second semiconductor layer is removed by etching in a step of forming the p-type semiconductor portion, the insulating layer which is the lower layer functions as an etching stopper, and the film thickness of the p-type semiconductor portion can be easily adjusted.Type: ApplicationFiled: June 20, 2016Publication date: February 2, 2017Inventors: Yasutaka NAKASHIBA, Shinichi WATANUKI
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Publication number: 20170031095Abstract: An SOI substrate includes a base substrate, a polycrystalline silicon layer formed on the base substrate, an insulating layer formed on the polycrystalline silicon layer, and a semiconductor layer formed on the insulating layer, and optical waveguides are formed in the semiconductor layer of the SOI substrate. Thus, by arranging the polycrystalline silicon layer under the insulating layer, the insulating layer can be made thin. Since the polycrystalline silicon layer includes a plurality of grains (amass of grains made of a single crystal Si), even when leakage of light is generated beyond the insulating layer, reflection (diffusion) of light can be suppressed. In addition, by arranging the polycrystalline silicon layer under the insulating layer, the insulating layer can be made thin, so that distortion of a substrate can be suppressed.Type: ApplicationFiled: June 21, 2016Publication date: February 2, 2017Inventors: Yasutaka NAKASHIBA, Shinichi WATANUKI
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Publication number: 20170023732Abstract: An interposer includes a plurality of identical functional blocks arranged in the x direction, for example, and the functional blocks include a first region mounting a semiconductor chip, a second region mounting a light emitting element chip, a third region mounting a light receiving element chip, and a plurality of silicon waveguides. Then, the second and third regions are arranged between the first region and a first side along the x direction of the interposer. In addition, the plurality of silicon waveguides are arranged between the second region and the first side, and between the third region and the first side, extending from the second region toward the first side and from the third region toward the first side and are not formed between the functional blocks adjacent in the x direction.Type: ApplicationFiled: June 19, 2016Publication date: January 26, 2017Inventors: Shinichi WATANUKI, Yasutaka NAKASHIBA
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Patent number: 9508662Abstract: A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device. In a cross-section perpendicular to an extending direction of an electrical signal transmission line, the electrical signal transmission line is surrounded by a shielding portion including a first noise cut wiring, second plugs, a first layer wiring, first plugs, a shielding semiconductor layer, first plugs, a first layer wiring, second plugs, and a second noise cut wiring, and the shielding portion is fixed to a reference potential. Thereby, the shielding portion blocks noise due to effects of a magnetic field or an electric field from the semiconductor substrate, which affects the electrical signal transmission line.Type: GrantFiled: August 17, 2015Date of Patent: November 29, 2016Assignee: Renesas Electronics CorporationInventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
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Publication number: 20160334573Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.Type: ApplicationFiled: May 11, 2016Publication date: November 17, 2016Inventors: Hiroyuki KUNISHIMA, Yasutaka NAKASHIBA, Masaru WAKABAYASHI, Shinichi WATANUKI
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Publication number: 20160282554Abstract: A semiconductor substrate, an insulating layer made of silicon oxide formed on the semiconductor substrate and a semiconductor layer made of silicon formed on the insulating layer are provided, and the semiconductor layer constitutes an optical waveguide in an optical signal transmission line section and an optical modulator in an optical modulation section. Also, the insulating layer is removed except for a part thereof to have a hollow structure with a cavity, and both side surfaces and a lower surface of each of the semiconductor layers constituting the optical waveguide and the optical modulator are exposed and covered with air.Type: ApplicationFiled: March 6, 2016Publication date: September 29, 2016Inventors: Shinichi WATANUKI, Atsuro INADA
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Publication number: 20160056115Abstract: A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device. In a cross-section perpendicular to an extending direction of an electrical signal transmission line, the electrical signal transmission line is surrounded by a shielding portion including a first noise cut wiring, second plugs, a first layer wiring, first plugs, a shielding semiconductor layer, first plugs, a first layer wiring, second plugs, and a second noise cut wiring, and the shielding portion is fixed to a reference potential. Thereby, the shielding portion blocks noise due to effects of a magnetic field or an electric field from the semiconductor substrate, which affects the electrical signal transmission line.Type: ApplicationFiled: August 17, 2015Publication date: February 25, 2016Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
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Publication number: 20160054521Abstract: Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region.Type: ApplicationFiled: August 17, 2015Publication date: February 25, 2016Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
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Patent number: 7370304Abstract: An LSI designing system includes a memory;, a database configured to store a layout layer definition file, and a control section configured to refer to the database to build up a plurality of layout layers in the memory based on the layout layer definition file. The plurality of layout layers are provided for extending directions of patterns in one of physical layers of an LSI to be formed. The control section divides each of the patterns into pattern structures based on the extending directions, and assigns each of the pattern structures to a corresponding one of the plurality of layout layers.Type: GrantFiled: July 15, 2005Date of Patent: May 6, 2008Assignee: NEC Electronics CorporationInventor: Shinichi Watanuki
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Publication number: 20070105053Abstract: Aiming at improving productivity of the semiconductor devices and at improving the product yield, a method of the present invention fabricates a semiconductor device by using, as a photomask, a first photomask 106 having a first rectangular pattern 104a obtained by dividing a mask pattern, and a second photomask 108 having a second rectangular pattern 104b obtained by dividing the mask pattern, wherein the method includes a first step processing a sacrificial film formed on a semiconductor substrate, using the first photomask 106 to thereby form therein a first rectangular pattern 104a; a second step processing the sacrificial film using the second photomask 108 to thereby form therein a second rectangular pattern 104b; and a third step etching the film formed on the semiconductor substrate, using, as a mask, the sacrificial film processed as having the rectangular pattern 104a and the second rectangular pattern 104b formed therein.Type: ApplicationFiled: October 24, 2006Publication date: May 10, 2007Inventors: Shinichi Watanuki, Toshinori Fukai
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Publication number: 20060015837Abstract: An LSI designing system includes a memory;, a database configured to store a layout layer definition file, and a control section configured to refer to the database to build up a plurality of layout layers in the memory based on the layout layer definition file. The plurality of layout layers are provided for extending directions of patterns in one of physical layers of an LSI to be formed. The control section divides each of the patterns into pattern structures based on the extending directions, and assigns each of the pattern structures to a corresponding one of the plurality of layout layers.Type: ApplicationFiled: July 15, 2005Publication date: January 19, 2006Inventor: Shinichi Watanuki
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Patent number: 6127267Abstract: A fabrication method of a semiconductor device is provided, which makes it possible to form a thin and elongated refractory-metal silicide layer while preventing the overgrowth phenomenon. This method is comprised of the steps (a) to (c). In the step (a), a first refractory metal film is formed on a silicon region. In the step (b), a second refractory metal film is formed on the first refractory metal film. The second refractory metal film contains a same refractory metal as the first refractory metal film and nitrogen. A stress of the second refractory metal film is controlled to be a specific value or lower. In the step (c), the first refractory metal film and the second refractory metal film are heat-treated in an atmosphere excluding nitrogen, thereby forming a refractory-metal silicide layer at an interface between the silicon region and the first refractory metal film due to silicidation reaction of the first refractory metal film with the silicon region.Type: GrantFiled: October 9, 1998Date of Patent: October 3, 2000Assignee: NEC CorporationInventors: Yoshihisa Matsubara, Takashi Ishigami, Yoshiaki Yamada, Shinichi Watanuki