Patents by Inventor Shinichi Yasuda
Shinichi Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11115024Abstract: An integrated circuit of an embodiment includes: a logic circuit; and a switch circuit, the logic circuit including: a first memory; a look-up table circuit having a first output terminal; a first selection circuit having a first input terminal connecting to the first output terminal, a second input terminal receiving scan input data, and a second output terminal, the first selection circuit selecting one of the first and second input terminals and connect the selected one to the second output terminal; a flip-flop having a third input terminal connected to the second and third output terminals; and a second selection circuit having a fourth and fifth input terminals connected to the third output terminal and the first output terminal respectively, and a fourth output terminal, the second selection circuit selecting one of the fourth and fifth input terminals and connect the selected one to the fourth output terminal.Type: GrantFiled: March 12, 2020Date of Patent: September 7, 2021Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masato Oda, Shinichi Yasuda
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Publication number: 20210083672Abstract: An integrated circuit of an embodiment includes: a logic circuit; and a switch circuit, the logic circuit including: a first memory; a look-up table circuit having a first output terminal; a first selection circuit having a first input terminal connecting to the first output terminal, a second input terminal receiving scan input data, and a second output terminal, the first selection circuit selecting one of the first and second input terminals and connect the selected one to the second output terminal; a flip-flop having a third input terminal connected to the second and third output terminals; and a second selection circuit having a fourth and fifth input terminals connected to the third output terminal and the first output terminal respectively, and a fourth output terminal, the second selection circuit selecting one of the fourth and fifth input terminals and connect the selected one to the fourth output terminal.Type: ApplicationFiled: March 12, 2020Publication date: March 18, 2021Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masato ODA, Shinichi YASUDA
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Patent number: 10707219Abstract: A semiconductor integrated circuit of an embodiment includes: first to fifth wiring lines; a first OTP memory element including a first and second terminals connected to the first and second wiring lines; a first p-channel transistor including a source and drain terminals connected to the first and third wiring line, and a gate terminal receiving a first control signal; a first n-channel transistor including a source and drain terminals connected to the first and fourth wiring lines, and a gate terminal receiving a second control signal; a second p-channel transistor including a source and drain terminals connected to the second and third wiring lines, and a gate terminal receiving a third control signal; and a second n-channel transistor including a source and drain terminals connected to the second and fifth wiring lines, and a gate terminal receiving a fourth control signal.Type: GrantFiled: March 8, 2019Date of Patent: July 7, 2020Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yinghao Ho, Masato Oda, Shinichi Yasuda
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Publication number: 20200083235Abstract: A semiconductor integrated circuit of an embodiment includes: first to fifth wiring lines; a first OTP memory element including a first and second terminals connected to the first and second wiring lines; a first p-channel transistor including a source and drain terminals connected to the first and third wiring line, and a gate terminal receiving a first control signal; a first n-channel transistor including a source and drain terminals connected to the first and fourth wiring lines, and a gate terminal receiving a second control signal; a second p-channel transistor including a source and drain terminals connected to the second and third wiring lines, and a gate terminal receiving a third control signal; and a second n-channel transistor including a source and drain terminals connected to the second and fifth wiring lines, and a gate terminal receiving a fourth control signal.Type: ApplicationFiled: March 8, 2019Publication date: March 12, 2020Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yinghao HO, Masato Oda, Shinichi Yasuda
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Patent number: 10559350Abstract: A memory circuit according to an embodiment includes: a first inverter circuit including a first p-channel MOS transistor and a first n-channel MOS transistor; a second inverter circuit cross-coupled with the first inverter and including a second p-channel MOS transistor and a second n-channel MOS transistor; a third n-channel MOS transistor in which one of a source and drain terminals is connected to a first output terminal of the first inverter circuit, and a gate terminal is connected to a first wiring line; a fourth n-channel MOS transistor connected to the third n-channel MOS transistor; a fifth n-channel MOS transistor in which one of a source and drain terminals is connected to a second output terminal of the second inverter circuit; and a sixth n-channel MOS transistor connected to the fifth n-channel MOS transistor.Type: GrantFiled: September 11, 2018Date of Patent: February 11, 2020Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masato Oda, Shinichi Yasuda
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Patent number: 10511020Abstract: An objective of the present invention is to provide a non-aqueous electrolyte secondary battery positive electrode active material formed from a lithium-nickel composite oxide which, while retaining high capacity and a high level of safety, has an excellent cycle characteristic by controlling reaction resistance and a method for producing it. [Solution] A lithium-nickel composite oxide is produced by steps (a) to (c) described below: (a) nickel hydroxide and/or nickel oxyhydroxide in a prescribed composition are sintered in a non-reducing atmosphere having 850° C. or lower to give nickel oxide; (b) after the nickel oxide and a lithium compound are mixed in a prescribed molar ratio, the mixture is sintered in an oxygen atmosphere at a temperature of 650 to 850° C.Type: GrantFiled: October 15, 2013Date of Patent: December 17, 2019Assignees: SUMITOMO METAL MINING CO., LTD., SANYO ELECTRIC CO., LTD.Inventors: Shin Imaizumi, Hideo Sasaoka, Shinichi Yasuda, Yutaka Kawatate, Takahiro Sakamoto
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Patent number: 10459692Abstract: According to one embodiment, a random number generator includes a first circuit which outputs a second oscillation signal having a predetermined duty ratio on the basis of a first oscillation signal, a second circuit which latches values on the basis of the second oscillation signal and a clock having a frequency lower than a frequency of the second oscillation signal, a third circuit which outputs a control signal on the basis of the values, and a fourth circuit which controls the first circuit on the basis of the control signal.Type: GrantFiled: September 13, 2016Date of Patent: October 29, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Takaya, Shinichi Yasuda, Tetsufumi Tanamoto, Shinobu Fujita
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Patent number: 10431306Abstract: A semiconductor integrated circuit according to an embodiment includes: first to third wiring lines; first memory elements disposed in a cross region between the first wiring lines and the second wiring lines; second memory elements disposed in a cross region between the first wiring lines and the third wiring lines; a first write control circuit connected to the first wiring lines: a first circuit connected to one of the second wiring lines and supplying a first potential; a second circuit connected to the other one of the second wiring lines and supplying a second potential lower than the first potential; SRAM cells connected to the third wiring lines; and a selection circuit including input terminals electrically connected to the first wiring lines and an output terminal, the selection circuit connecting one of the input terminals to the output terminal in accordance with an input signal.Type: GrantFiled: March 6, 2018Date of Patent: October 1, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Shinichi Yasuda, Masato Oda, Kosuke Tatsumura
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Patent number: 10424377Abstract: A semiconductor integrated circuit according to an embodiment includes: first to third wirings; first current limiters corresponding to the first wirings; second current limiters corresponding to the second wirings; third current limiters corresponding to the third wirings; first drivers corresponding to the first current limiters; second drivers corresponding to the second current limiters; third drivers corresponding to the third current limiters; and a first array and a second array, wherein the first array comprising: fourth wirings corresponding to the first wirings; fifth wirings corresponding to the second wirings; first transistors corresponding to the first wirings; second transistors corresponding to the second wirings; and first resistive change elements arranged in intersecting areas of the fourth wirings and the fifth wirings, respectively, the first resistive change elements including a first terminal connected to corresponding one of the fourth wirings and a second terminal connected to correspType: GrantFiled: February 28, 2018Date of Patent: September 24, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yinghao Ho, Masato Oda, Kosuke Tatsumura, Shinichi Yasuda
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Publication number: 20190287610Abstract: A memory circuit according to an embodiment includes: a first inverter circuit including a first p-channel MOS transistor and a first n-channel MOS transistor; a second inverter circuit cross-coupled with the first inverter and including a second p-channel MOS transistor and a second n-channel MOS transistor; a third n-channel MOS transistor in which one of a source and drain terminals is connected to a first output terminal of the first inverter circuit, and a gate terminal is connected to a first wiring line; a fourth n-channel MOS transistor connected to the third n-channel MOS transistor; a fifth n-channel MOS transistor in which one of a source and drain terminals is connected to a second output terminal of the second inverter circuit; and a sixth n-channel MOS transistor connected to the fifth n-channel MOS transistor.Type: ApplicationFiled: September 11, 2018Publication date: September 19, 2019Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masato ODA, Shinichi YASUDA
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Patent number: 10360333Abstract: A configuration memory circuit according to an embodiment includes: a first and second wirings; and a first to eighth transistors, the first and fourth transistors having a first-conductive-type, the second, third, fifth, and sixth transistors having a second-conductive-type, the first to third transistors being connected in series, the fourth to sixth transistors being connected in series, gates of the first and third transistors being connected to the first wiring, one of a source and a drain of the seventh transistor, and the first wiring, a gate of the second transistor being connected to a third wiring, gates of the fourth and sixth transistors being connected to the second wiring, one of a source and a drain of the eighth transistor, and the second wiring, a gate of the fifth transistor being connected to the third wiring, gates of the seventh and eighth transistors being connected to a fifth wiring.Type: GrantFiled: September 12, 2018Date of Patent: July 23, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Shinichi Yasuda, Masato Oda
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Publication number: 20190080758Abstract: A semiconductor integrated circuit according to an embodiment includes: first to third wirings; first current limiters corresponding to the first wirings; second current limiters corresponding to the second wirings; third current limiters corresponding to the third wirings; first drivers corresponding to the first current limiters; second drivers corresponding to the second current limiters; third drivers corresponding to the third current limiters; and a first array and a second array, wherein the first array comprising: fourth wirings corresponding to the first wirings; fifth wirings corresponding to the second wirings; first transistors corresponding to the first wirings; second transistors corresponding to the second wirings; and first resistive change elements arranged in intersecting areas of the fourth wirings and the fifth wirings, respectively, the first resistive change elements including a first terminal connected to corresponding one of the fourth wirings and a second terminal connected to correspType: ApplicationFiled: February 28, 2018Publication date: March 14, 2019Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yinghao HO, Masato ODA, Kosuke TATSUMURA, Shinichi YASUDA
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Patent number: 10218518Abstract: An authentication server according to embodiments performs statistical processing on a plurality of pieces of ID data acquired from an electronic device including a PUF circuit generating the pieces of ID data (S1052 to S1071), determines whether the plurality of pieces of ID data are physical random numbers based on a result of the statistical processing (S1072), and when the plurality of pieces of ID data are determined to be physical random numbers, recognizes the result of authentication of the electronic device as a success of authentication (S1073), and when the plurality of pieces of ID data are determined not to be physical random numbers, recognizes a result of authentication of the electronic device as a failure of authentication (S1074).Type: GrantFiled: February 27, 2017Date of Patent: February 26, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Masafumi Mori, Takao Marukame
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Publication number: 20190043581Abstract: A semiconductor integrated circuit according to an embodiment includes: first to third wiring lines; first memory elements disposed in a cross region between the first wiring lines and the second wiring lines; second memory elements disposed in a cross region between the first wiring lines and the third wiring lines; a first write control circuit connected to the first wiring lines: a first circuit connected to one of the second wiring lines and supplying a first potential; a second circuit connected to the other one of the second wiring lines and supplying a second potential lower than the first potential; SRAM cells connected to the third wiring lines; and a selection circuit including input terminals electrically connected to the first wiring lines and an output terminal, the selection circuit connecting one of the input terminals to the output terminal in accordance with an input signal.Type: ApplicationFiled: March 6, 2018Publication date: February 7, 2019Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shinichi Yasuda, Masato Oda, Kosuke Tatsumura
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Patent number: 10175947Abstract: According to an embodiment, an arithmetic device is configured to receive M input signals each representing a two-state value and M coefficients to output an output signal representing a two-state value. The device includes a positive-side current source, a negative-side current source, M cross switches, a coefficient memory unit, and a comparator. The positive-side current source is configured to output a first voltage corresponding to a value of 1/L of the current output from a positive-side terminal. The negative-side current source is configured to output a second voltage corresponding to a value of 1/L of the current output from a negative-side terminal. The memory unit includes M cells corresponding to the respective M coefficients. The comparator is configured to output an output signal having a value corresponding to a comparison result of the first voltage with the second voltage. Each M cell includes a first resistor and a second resistor.Type: GrantFiled: February 20, 2018Date of Patent: January 8, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Takao Marukame, Yoshihiro Ueda, Shinji Miyano, Shinichi Yasuda, Yoshifumi Nishi, Mari Matsumoto
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Patent number: 10127980Abstract: An integrated circuit according to an embodiment includes: first and second wiring lines; a memory device including a first and second terminals connected to the first and second wiring line respectively; a first transistor including a high-k metal gate; a first circuit applying a first write voltage between the first and the second terminals, and switch the resistance of the memory device from a high-resistance state to a low-resistance state; a second circuit reading the resistance of the memory device, and comparing a read value of the resistance with a predetermined value; a third circuit lowering a threshold voltage of the first transistor when the read value of the resistance is greater than the predetermined value; a fourth circuit applying a second write voltage between the first and second terminals after the threshold voltage is lowered; and a fifth circuit raising the threshold voltage of the first transistor.Type: GrantFiled: September 13, 2017Date of Patent: November 13, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Mari Matsumoto, Shinichi Yasuda
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Patent number: 10090049Abstract: An integrated circuit according to an embodiment includes: resistive change elements disposed in intersection regions between first and second wiring lines; a first driver driving the first wiring lines; a second driver driving the second wiring lines; a control circuit controlling the first and second drivers; first current limiter circuits corresponding to the first wiring lines, each of the first current circuits each limiting a maximum current flowing in corresponding one of the first wiring lines to a value not greater than one of a first to third current values; and second current limiter circuits corresponding to the second wiring lines, the second current limiter circuits each limiting a maximum current flowing in corresponding one of the second wiring lines to a value not greater than one of the first to third current value, the limiting current of the selected element being higher than that of the unselected element.Type: GrantFiled: September 11, 2017Date of Patent: October 2, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Yinghao Ho, Shinichi Yasuda
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Publication number: 20180276557Abstract: According to one embodiment, a quantum annealing machine 1 includes a quantum bit array 21 which includes a plurality of cells (quantum bits) 211 respectively including a floating gate 105, and a controller 10 which executes writing of data in the plurality of cells 211, and temporally controls tunneling of an electric charge with respect to the floating gate 105.Type: ApplicationFiled: September 11, 2017Publication date: September 27, 2018Applicant: Toshiba Memory CorporationInventors: Tetsufumi Tanamoto, Yusuke Higashi, Takao Marukame, Shinichi Yasuda, Jun Deguchi
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Publication number: 20180261287Abstract: An integrated circuit according to an embodiment includes: first and second wiring lines; a memory device including a first and second terminals connected to the first and second wiring line respectively; a first transistor including a high-k metal gate; a first circuit applying a first write voltage between the first and the second terminals, and switch the resistance of the memory device from a high-resistance state to a low-resistance state; a second circuit reading the resistance of the memory device, and comparing a read value of the resistance with a predetermined value; a third circuit lowering a threshold voltage of the first transistor when the read value of the resistance is greater than the predetermined value; a fourth circuit applying a second write voltage between the first and second terminals after the threshold voltage is lowered; and a fifth circuit raising the threshold voltage of the first transistor.Type: ApplicationFiled: September 13, 2017Publication date: September 13, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mari MATSUMOTO, Shinichi YASUDA
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Publication number: 20180151225Abstract: An integrated circuit according to an embodiment includes: resistive change elements disposed in intersection regions between first and second wiring lines; a first driver driving the first wiring lines; a second driver driving the second wiring lines; a control circuit controlling the first and second drivers; first current limiter circuits corresponding to the first wiring lines, each of the first current circuits each limiting a maximum current flowing in corresponding one of the first wiring lines to a value not greater than one of a first to third current values; and second current limiter circuits corresponding to the second wiring lines, the second current limiter circuits each limiting a maximum current flowing in corresponding one of the second wiring lines to a value not greater than one of the first to third current value, the limiting current of the selected element being higher than that of the unselected element.Type: ApplicationFiled: September 11, 2017Publication date: May 31, 2018Inventors: Yinghao HO, Shinichi YASUDA