Patents by Inventor Shinichi Yoshida
Shinichi Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10882290Abstract: Provided are a packaging sheet and a packaging container where it is unnecessary to paste a printed label and disappearance or color development due to friction or the like after thermal printing do not occur. The packaging sheet includes a heat seal layer 10 for thermally welding by heating, a heat-sensitive layer 40 including a color developing material that develops a color by heating, and a base material layer 70 that secures the strength and protects the heat-sensitive layer 40. The heat seal layer 10, the heat-sensitive layer 40, and the base material layer 70 are provided in this order from a back surface side in a thickness direction. The packaging sheet is transparent before the heat-sensitive layer 40 develops the color.Type: GrantFiled: January 14, 2016Date of Patent: January 5, 2021Assignee: Osaka Sealing Printing Co., LTD.Inventors: Shinichi Ono, Takayuki Kimura, Hidenao Takeuchi, Masahiko Yoshida, Hidenobu Harima
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Patent number: 10866733Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.Type: GrantFiled: June 26, 2017Date of Patent: December 15, 2020Assignee: Toshiba Memory CorporationInventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida, Hiroshi Murayama
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Patent number: 10858392Abstract: An affinity separation matrix includes a water-insoluble base material; and a ligand that is immobilized on the water-insoluble base material, wherein the ligand is an antibody ? chain variable region-binding peptide comprising B5 domain of Protein L derived from Peptostreptococcus magnus 312 strain or a part thereof.Type: GrantFiled: July 26, 2017Date of Patent: December 8, 2020Assignee: KANEKA CORPORATIONInventors: Shinichi Yoshida, Dai Murata
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Patent number: 10844112Abstract: A method for purifying an antibody or an antibody fragment containing ?-chain variable region includes adsorbing at least one of the antibody or the antibody fragment onto an affinity separation matrix by contacting a liquid sample with the affinity separation matrix, washing the affinity separation matrix to remove impurities, and separating the at least one of the antibody or the antibody fragment from the affinity separation matrix by using an acetate buffer. The liquid sample includes the at least one of the antibody or the antibody fragment. The affinity separation matrix includes a water-insoluble carrier and a ligand selected from the group consisting of Protein L, a variant of Protein L, a domain of Protein L, and a variant of the domain. The ligand is immobilized on the water-insoluble carrier.Type: GrantFiled: November 7, 2018Date of Patent: November 24, 2020Assignee: KANEKA CORPORATIONInventors: Dai Murata, Shinichi Yoshida, Kazunobu Minakuchi
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Publication number: 20200363996Abstract: According to one embodiment, a memory system receives, from a host, a write request including a first identifier associated with one write destination block and storage location information indicating a location in a write buffer on a memory of the host in which first data to be written is stored. When the first data is to be written to a nonvolatile memory, the memory system obtains the first data from the write buffer by transmitting a transfer request including the storage location information to the host, transfers the first data to the nonvolatile memory, and writes the first data to the one write destination block.Type: ApplicationFiled: August 4, 2020Publication date: November 19, 2020Inventors: Shinichi Kanno, Hideki Yoshida
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Publication number: 20200364145Abstract: According to one embodiment, an information processing apparatus stores first data to be written to one destination block of a nonvolatile memory in a write buffer on a memory of the information processing apparatus. The information processing apparatus transmits, to a storage device, a write request including a first identifier associated with the one write destination block and storage location information indicating a location in the write buffer in which the first data is stored. The information processing apparatus transfers the first data from the write buffer to the storage device every time a transfer request including the storage location information is received from the storage device.Type: ApplicationFiled: August 7, 2020Publication date: November 19, 2020Inventors: Shinichi Kanno, Hideki Yoshida
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Publication number: 20200354696Abstract: A mutant PHA synthetase which enables production of a PHA copolymer with a high or low 3HH ratio while maintaining PHA productivity. The mutant PHA synthetase is a mutant polyhydroxyalkanoate synthetase having an amino acid sequence having 85% or more sequence identity with the amino acid sequence of SEQ ID NO: 1 and having at least one of the following mutations (a) to (c): (a): mutation of substitution of serine at 389th position from N-terminus of the amino acid sequence of SEQ ID NO: 1 with an amino acid other than serine; (b): mutation of substitution of leucine at 436th position from the N-terminus of the amino acid sequence of SEQ ID NO: 1 with an amino acid other than leucine; and (c): mutation of deletion of 11 or more and 19 or less amino acid residues from C-terminus of the amino acid sequence of SEQ ID NO: 1.Type: ApplicationFiled: January 10, 2019Publication date: November 12, 2020Applicant: KANEKA CORPORATIONInventors: Shingo KOBAYASHI, Shinichi YOSHIDA, Shunsuke SATO, Naoaki YAOKA
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Patent number: 10824217Abstract: According to one embodiment, a storage includes a nonvolatile memory and a controller configured to control the nonvolatile memory. The storage is supplied with first power from a power supply unit. The controller is configured to change power supplied from the power supply unit from the first power to second power based on a power control command transmitted from a host. The power control command includes a first parameter identifying the storage and a second parameter indicative of the second power.Type: GrantFiled: December 20, 2018Date of Patent: November 3, 2020Assignee: Toshiba Memory CorporationInventors: Naoki Sawai, Hiroshi Murayama, Hiroshi Nishimura, Shinichi Kanno, Hideki Yoshida
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Publication number: 20200341681Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.Type: ApplicationFiled: July 14, 2020Publication date: October 29, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Shinichi KANNO, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
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Patent number: 10808013Abstract: A first immunoglobulin ? chain variable region-binding peptide includes an amino acid sequence of SEQ ID NO: 21 with substitution of one or more amino acid residues at the 15th position, the 16th position, the 17th position or the 18th position, wherein an acid dissociation pH thereof is shifted to a neutral side. A second immunoglobulin ? chain variable region-binding peptide further includes deletion, substitution and/or addition of 1-20 amino acid residues at positions other than the 15th position, the 16th position, the 17th position and the 18th position. A third immunoglobulin ? chain variable region-binding peptide includes an amino acid sequence with a sequence identity of 80% or more to the amino acid sequence of the first immunoglobulin ? chain variable region-binding peptide.Type: GrantFiled: July 26, 2017Date of Patent: October 20, 2020Assignee: KANEKA CORPORATIONInventor: Shinichi Yoshida
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Publication number: 20200325890Abstract: An air compressor includes: a motor; a compression mechanism that is driven by the motor and that is configured to generate compressed air; a tank that is configured to store the generated compressed air; a load acquisition part that is configured to acquire a load applied to the compression mechanism; and a control part that is configured to control a rotation of the motor. The control part is configured to perform control for changing a TN characteristic of the motor in response to the load of the compression mechanism acquired by the load acquisition part.Type: ApplicationFiled: April 10, 2020Publication date: October 15, 2020Applicant: MAX CO., LTD.Inventors: Shinichi OKUBO, Tsutomu YOSHIDA
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Patent number: 10800754Abstract: Provided is a heterocyclic amide compound that may have a PRS inhibitory action and is expected to be useful as a prophylactic or therapeutic agent for PRS associated diseases and the like including cancer. A compound represented by the following formula (I): wherein each symbol is as described in the DESCRIPTION, or a salt thereof.Type: GrantFiled: September 14, 2017Date of Patent: October 13, 2020Assignee: TAKEDA PHARMACEUTICAL COMPANY LIMITEDInventors: Takaharu Hirayama, Yasuhiro Hirata, Yusuke Tominari, Naoki Iwamura, Yusuke Sasaki, Moriteru Asano, Terufumi Takagi, Masanori Okaniwa, Masato Yoshida, Shinichi Imamura
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Publication number: 20200310961Abstract: According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.Type: ApplicationFiled: June 12, 2020Publication date: October 1, 2020Inventors: Hideki Yoshida, Shinichi Kanno
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Patent number: 10789167Abstract: According to one embodiment, an information processing apparatus stores first data to be written to one destination block of a nonvolatile memory in a write buffer on a memory of the information processing apparatus. The information processing apparatus transmits, to a storage device, a write request including a first identifier associated with the one write destination block and storage location information indicating a location in the write buffer in which the first data is stored. The information processing apparatus transfers the first data from the write buffer to the storage device every time a transfer request including the storage location information is received from the storage device.Type: GrantFiled: June 11, 2018Date of Patent: September 29, 2020Assignee: Toshiba Memory CorporationInventors: Shinichi Kanno, Hideki Yoshida
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Patent number: 10774115Abstract: A first Fab region-binding peptide includes an amino acid sequence selected from the group consisting of SEQ ID NOs: 1 to 5 with substitution of one or more amino acid residues at the 17th position and the 36th position, wherein an acid dissociation pH thereof is shifted to a neutral side. A second Fab region-binding peptide further includes deletion, substitution and/or addition of one or more amino acid residues at positions other than the 17th position and the 36th position. A third Fab region-binding peptide includes an amino acid sequence with a sequence identity of 80% or more to the amino acid sequence of the first Fab region-binding peptide.Type: GrantFiled: August 25, 2017Date of Patent: September 15, 2020Assignee: KANEKA CORPORATIONInventor: Shinichi Yoshida
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Patent number: 10773311Abstract: An object of the present invention is to provide a phosphorus-containing copper powder with good volume resistivity and a small carbon content by suppressing an oxygen content to a relatively low value even if a particle size is made small, and a method for producing the same. In the phosphorus-containing copper powder containing phosphorus, a ratio of an oxygen content (wt. %) to a BET specific surface area (m2/g) (oxygen content/BET specific surface area) is 0.90 wt. %·g/m2 or less, a divalent copper compound is present on a surface of particles constituting the phosphorus-containing copper powder, a carbon content is 0.10 wt. % or less, and D50 is 7.11 ?m or less.Type: GrantFiled: August 18, 2016Date of Patent: September 15, 2020Assignee: DOWA ELECTRONICS MATERIALS CO., LTD.Inventors: Kenichi Inoue, Atsushi Ebara, Masahiro Yoshida, Kyoso Masuda, Takahiro Yamada, Shinichi Uchiyama
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Publication number: 20200286937Abstract: The present technology relates to a solid-state imaging element configured so that pixels can be more reliably separated, a method for manufacturing the solid-state imaging element, and an electronic apparatus. The solid-state imaging element includes a photoelectric converter, a first separator, and a second separator. The photoelectric converter is configured to perform photoelectric conversion of incident light. The first separator configured to separate the photoelectric converter is formed in a first trench formed from a first surface side. The second separator configured to separate the photoelectric converter is formed in a second trench formed from a second surface side facing a first surface. The present technology is applicable to an individual imaging element mounted on, e.g., a camera and configured to acquire an image of an object.Type: ApplicationFiled: May 18, 2020Publication date: September 10, 2020Applicant: SONY CORPORATIONInventors: Hideyuki HONDA, Tetsuya UCHIDA, Toshifumi WAKANO, Yusuke TANAKA, Yoshiharu KUDOH, Hirotoshi NOMURA, Tomoyuki HIRANO, Shinichi YOSHIDA, Yoichi UEDA, Kosuke NAKANISHI
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Patent number: 10768858Abstract: According to one embodiment, a memory system receives, from a host, a write request including a first identifier associated with one write destination block and storage location information indicating a location in a write buffer on a memory of the host in which first data to be written is stored. When the first data is to be written to a nonvolatile memory, the memory system obtains the first data from the write buffer by transmitting a transfer request including the storage location information to the host, transfers the first data to the nonvolatile memory, and writes the first data to the one write destination block.Type: GrantFiled: June 11, 2018Date of Patent: September 8, 2020Assignee: Toshiba Memory CorporationInventors: Shinichi Kanno, Hideki Yoshida
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Patent number: 10761771Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.Type: GrantFiled: March 13, 2019Date of Patent: September 1, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
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Patent number: D897496Type: GrantFiled: February 1, 2019Date of Patent: September 29, 2020Assignee: SMC CORPORATIONInventors: Shinichi Yoshimura, Masaru Yoshida, Kenichi Matsumura, Yoichi Morodomi