Patents by Inventor Shinichiro Kimura
Shinichiro Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120018807Abstract: In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.Type: ApplicationFiled: January 18, 2010Publication date: January 26, 2012Applicant: HITACHI, LTD.Inventors: Ryuta Tsuchiya, Nobuyuki Sugii, Yusuke Morita, Hiroyuki Yoshimoto, Takashi Ishigaki, Shinichiro Kimura
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Patent number: 8084810Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.Type: GrantFiled: December 29, 2009Date of Patent: December 27, 2011Assignee: Renesas Electronics CorporationInventors: Digh Hisamoto, Shinichiro Kimura, Kan Yasui, Nozomu Matsuzaki
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Patent number: 8076709Abstract: In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.Type: GrantFiled: September 1, 2010Date of Patent: December 13, 2011Assignee: Renesas Electronics CorporationInventors: Tetsuya Ishimaru, Digh Hisamoto, Kan Yasui, Shinichiro Kimura
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Patent number: 8064261Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.Type: GrantFiled: May 25, 2010Date of Patent: November 22, 2011Assignee: Renesas Electronics CorporationInventors: Digh Hisamoto, Kan Yasui, Tetsuya Ishimaru, Shinichiro Kimura, Daisuke Okada
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Patent number: 8030668Abstract: A light emitting diode demonstrating high luminescence efficiency and comprising a Group IV semiconductor such as silicon or germanium equivalent thereto as a basic component formed on a silicon substrate by a prior art silicon process, and a fabricating method of waveguide thereof are provided. The light emitting diode of the invention comprises a first electrode for implanting electrons, a second electrode for implanting holes, and a light emitting section electrically connected to the first and the second electrode, wherein the light emitting section is made out of single crystalline silicon and has a first surface and a second surface facing the first surface, wherein with respect to plane orientation (100) of the first and second surfaces, the light emitting section crossing at right angles to the first and second surfaces is made thinner, and wherein a material having a high refractive index is arranged around the thin film section.Type: GrantFiled: November 6, 2007Date of Patent: October 4, 2011Assignee: Hitachi, Ltd.Inventors: Digh Hisamoto, Shinichi Saito, Shinichiro Kimura
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Publication number: 20110195566Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.Type: ApplicationFiled: April 15, 2011Publication date: August 11, 2011Applicant: RENESAS ELECTRONCS CORPORATIONInventors: Takashi ISHIGAKI, Ryuta TSUCHIYA, Yusuke MORITA, Nobuyuki SUGII, Shinichiro KIMURA, Toshiaki IWAMATSU
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Patent number: 7978212Abstract: Disclosed is a disk label printer that includes a slot-in type optical disk driving mechanism and a printing mechanism integrated with each other, has a small size, and smoothly transfers optical disks. The disclosed disk label printer includes: a case that has a slot through which an optical disk is inserted or ejected formed therein; an optical disk driving mechanism that is provided in the case and writes and/or reads signals to and/or from the optical disk mounted to a disk mounting portion; and a printing mechanism that is provided in the case and includes a thermal head which prints a desired image on a label surface of the optical disk. The printing mechanism is provided on a transfer path of the optical disk toward the optical disk driving mechanism between the slot and the optical disk driving mechanism.Type: GrantFiled: June 18, 2008Date of Patent: July 12, 2011Assignee: Alps Electric Co., Ltd.Inventors: Hiroyoshi Zama, Takashi Goto, Mitsuo Makino, Shinichi Sagawai, Mitsuaki Yamazaki, Eihin Setsu, Hisashi Hoshino, Tomohiro Osumi, Shinichiro Kimura
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Patent number: 7935597Abstract: Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.Type: GrantFiled: October 26, 2010Date of Patent: May 3, 2011Assignee: Renesas Electronics CorporationInventors: Yasuhiro Shimamoto, Digh Hisamoto, Tetsuya Ishimaru, Shinichiro Kimura
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Publication number: 20110039385Abstract: Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.Type: ApplicationFiled: October 26, 2010Publication date: February 17, 2011Inventors: Yasuhiro Shimamoto, Digh Hisamoto, Tetsuya Ishimaru, Shinichiro Kimura
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Patent number: 7872298Abstract: Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.Type: GrantFiled: July 13, 2007Date of Patent: January 18, 2011Assignee: Renesas Electronics CorporationInventors: Yasuhiro Shimamoto, Digh Hisamoto, Tetsuya Ishimaru, Shinichiro Kimura
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Publication number: 20100322013Abstract: In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.Type: ApplicationFiled: September 1, 2010Publication date: December 23, 2010Inventors: Tetsuya Ishimaru, Digh Hisamoto, Kan Yasui, Shinichiro Kimura
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Patent number: 7847343Abstract: Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.Type: GrantFiled: February 10, 2009Date of Patent: December 7, 2010Assignee: Renesas Electronics CorporationInventors: Digh Hisamoto, Kan Yasui, Shinichiro Kimura, Tetsuya Ishimaru
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Patent number: 7847331Abstract: In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.Type: GrantFiled: January 10, 2005Date of Patent: December 7, 2010Assignee: Renesas Electronics CorportionInventors: Tetsuya Ishimaru, Digh Hisamoto, Kan Yasui, Shinichiro Kimura
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Publication number: 20100258869Abstract: An n well and a p well disposed at a predetermined interval on a main surface of a SOI substrate with a thin BOX layer are formed, and an nMIS formed on the p well has a pair of n-type source/drain regions formed on semiconductor layers stacked on a main surface of the SOI layer at a predetermined distance, a gate insulating film, a gate electrode and sidewalls sandwiched between the pair of n-type source/drain regions. A device isolation is formed between the n well and the p well, and a side edge portion of the device isolation extends toward a gate electrode side more than a side edge portion of the n-type source/drain region (sidewall of the BOX layer).Type: ApplicationFiled: April 9, 2010Publication date: October 14, 2010Inventors: Yusuke MORITA, Ryuta Tsuchiya, Takashi Ishigaki, Hiroyuki Yoshimoto, Nobuyuki Sugii, Shinichiro Kimura
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Publication number: 20100258872Abstract: A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.Type: ApplicationFiled: April 8, 2010Publication date: October 14, 2010Inventors: Nobuyuki SUGII, Ryuta TSUCHIYA, Shinichiro KIMURA, Takashi ISHIGAKI, Yusuke MORITA, Hiroyuki YOSHIMOTO
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Publication number: 20100232231Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.Type: ApplicationFiled: May 25, 2010Publication date: September 16, 2010Inventors: Digh HISAMOTO, Kan Yasui, Tetsuya Ishimaru, Shinichiro Kimura, Daisuke Okada
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Patent number: 7751255Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.Type: GrantFiled: September 19, 2008Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Digh Hisamoto, Kan Yasui, Tetsuya Ishimaru, Shinichiro Kimura, Daisuke Okada
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Publication number: 20100135080Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.Type: ApplicationFiled: December 29, 2009Publication date: June 3, 2010Inventors: Digh HISAMOTO, Shinichiro Kimura, Kan Yasui, Nozomu Matsuzaki
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Publication number: 20100097246Abstract: An input device includes a plurality of manipulation portions; an input function portion manipulated by the manipulation portions to perform an input function; a light guiding sheet facing the rear side of the plurality of manipulation portions; and a light source applying light into the light guiding sheet, wherein a rear surface opposite to a front surface of the light guiding sheet facing the manipulation portions is provided with a plurality of concave portions which is depressed to the inside of the light guiding sheet, wherein each concave portion has a circular opening and an inner surface which is a smooth concave curve surface, and wherein light propagated through the inside of the light guiding sheet is reflected by the inner surface toward the inside of the light guiding sheet, and the light is applied from the front surface of the light guiding sheet to the manipulation portions.Type: ApplicationFiled: October 15, 2009Publication date: April 22, 2010Applicant: ALPS ELECTRIC CO., LTD.Inventors: Kazutoshi WATANABE, Hideaki Nagakubo, Takenobu Kimura, Koichi Yamamoto, Katsuyki Katayama, Naomi Sato, Naoya Akiyama, Shinichiro Kimura, Masahiro Ishida, Naoki Yamada, Keiji Takagi, Toshinobu Hosaka
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Publication number: 20100084709Abstract: When a bulk silicon substrate and an SOI substrate are used separately, a board area is increased and so it is impossible to reduce the size of a semiconductor device as a whole. On the other hand, when an SOI-type MISFET and a bulk-type MISFET are formed on a same substrate, the SOI-type MISFET and the bulk-type MISFET should be formed in separate steps respectively, and thus the process gets complicated. A single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) are used, and well diffusion layer regions, drain regions, gate insulating films and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in same steps. Since the bulk-type MISFET and the SOI-type MISFET can be formed on the same substrate, the board area can be reduced.Type: ApplicationFiled: June 30, 2006Publication date: April 8, 2010Inventors: Ryuta Tsuchiya, Shinichiro Kimura