Patents by Inventor Shinichiro Matsunaga

Shinichiro Matsunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11520315
    Abstract: Provided is a production system including: a plurality of industrial machines each configured to execute a process program for executing a predetermined process, and to perform at least one of refer or change of a machine variable; a controller configured to execute a system program for causing each of the plurality of industrial machines to operate based on an execution order specified for a plurality of predetermined processes, and to perform at least one of refer or change of a system variable; a storage configured to store conversion data for converting between the machine variable of each of the plurality of industrial machines and the system variable; and a circuitry configured to perform conversion between the machine variable of the each of the plurality of industrial machines and the system variable based on the conversion data of the each of the plurality of industrial machines.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: December 6, 2022
    Assignee: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Naoki Mizuno, Shinichiro Obata, Jongbeom Park, Aya Matsunaga
  • Publication number: 20220276630
    Abstract: A data collection system for an industrial machine, the data collection system comprising circuitry configured to: collect collection data relating to the industrial machine based on a predetermined collection setting; identify the predetermined collection setting based on identification information associated with the collection data; and execute parse processing relating to the collection data based on the identified predetermined collection setting.
    Type: Application
    Filed: February 24, 2022
    Publication date: September 1, 2022
    Inventors: Takeshi NAGATA, Tomoyuki NAKAMURA, Aya MATSUNAGA, Shinichiro OBATA, Ryosuke NISHIDA
  • Publication number: 20220254919
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, third semiconductor regions of the second conductivity type, provided in the second semiconductor layer at positions facing the first semiconductor regions in a depth direction and having an impurity concentration higher than an impurity concentration of the second semiconductor layer, trenches, gate insulating films, gate electrodes, a first electrode, a second electrode, and third electrodes. The third electrodes form Schottky junctions with the second semiconductor layer and are provided on the surface of portions of the second semiconductor layer free of the third semiconductor regions.
    Type: Application
    Filed: December 30, 2021
    Publication date: August 11, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Shinichiro MATSUNAGA
  • Publication number: 20220123112
    Abstract: A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 1×1015/cm3.
    Type: Application
    Filed: November 30, 2021
    Publication date: April 21, 2022
    Applicants: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi TAWARA, Tomonori MIZUSHIMA, Shinichiro MATSUNAGA, Kensuke TAKENAKA, Manabu TAKEI, Hidekazu TSUCHIDA, Kouichi MURATA, Akihiro KOYAMA, Koji NAKAYAMA, Mitsuru SOMETANI, Yoshiyuki YONEZAWA, Yuji KIUCHI
  • Patent number: 11251291
    Abstract: A silicon carbide semiconductor device includes first semiconductor areas and second semiconductor areas. The first semiconductor areas have a first semiconductor layer of a second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, gate electrodes, and first electrodes. The second semiconductor areas have the first semiconductor layer, the second semiconductor layer, third semiconductor regions of the second conductivity type, the gate electrodes, and the first electrodes. The first semiconductor regions include low- impurity-concentration regions and high-impurity-concentration regions. The third semiconductor regions have a potential equal to that of the first electrodes. The first semiconductor regions are connected to the third semiconductor regions by MOS structures.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: February 15, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shinichiro Matsunaga
  • Publication number: 20210167196
    Abstract: A silicon carbide semiconductor device includes first semiconductor areas and second semiconductor areas. The first semiconductor areas have a first semiconductor layer of a second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, gate electrodes, and first electrodes. The second semiconductor areas have the first semiconductor layer, the second semiconductor layer, third semiconductor regions of the second conductivity type, the gate electrodes, and the first electrodes. The first semiconductor regions include low- impurity-concentration regions and high-impurity-concentration regions. The third semiconductor regions have a potential equal to that of the first electrodes. The first semiconductor regions are connected to the third semiconductor regions by MOS structures.
    Type: Application
    Filed: November 18, 2020
    Publication date: June 3, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Shinichiro MATSUNAGA
  • Patent number: 10510543
    Abstract: A semiconductor device includes an n?-type drift layer of an formed on an n+-type SiC substrate; a p-type layer provided on a surface opposite that facing the n+-type SiC substrate; and an n-type buffer layer provided, as a recombination promoting layer, between the n?-type drift layer and the n+-type SiC substrate, the n-type buffer layer having an impurity concentration higher than that of the n?-type drift layer. In the buffer layer, as a recombination site, a defect energy-level is introduced at a high concentration of 1×1012/cm3 or higher. The buffer layer promotes internal electron-hole recombination and without applying high energy to BPDs at an interface of the buffer layer and the SiC substrate, may reduce the amount of recombination near the interface even at a current density equivalent to that of a conventional structure and thereby, prevents characteristics degradation at the time of operation.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shinichiro Matsunaga
  • Publication number: 20190103462
    Abstract: For example, a pin diode is constituted by a silicon carbide epitaxial substrate in which silicon carbide epitaxial layers constituting an n-type buffer region, an n?-type drift region, and a p++-type anode region are sequentially formed by epitaxial growth on a front surface of an n+-type silicon carbide substrate. The n?-type drift region has an n-type impurity concentration is, for example, about 1×1014/cm3 to 1×1016/cm3. The n?-type drift region has a boron concentration that is substantially lower than an n-type impurity concentration of the n?-type drift region and that, for example, is about 1×1014/cm3 or less. During epitaxial growth of the n?-type drift region, automatic doping of boron to the n?-type drift region is suppressed, whereby the boron concentration of the n?-type drift region is reduced and the n?-type drift region in which no traps are present is formed.
    Type: Application
    Filed: August 31, 2018
    Publication date: April 4, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Shinichiro MATSUNAGA
  • Publication number: 20180286683
    Abstract: A semiconductor device includes an n?-type drift layer of an formed on an n+-type SiC substrate; a p-type layer provided on a surface opposite that facing the n+-type SiC substrate; and an n-type buffer layer provided, as a recombination promoting layer, between the n?-type drift layer and the n+-type SiC substrate, the n-type buffer layer having an impurity concentration higher than that of the n?-type drift layer. In the buffer layer, as a recombination site, a defect energy-level is introduced at a high concentration of 1×1012/cm3 or higher. The buffer layer promotes internal electron-hole recombination and without applying high energy to BPDs at an interface of the buffer layer and the SiC substrate, may reduce the amount of recombination near the interface even at a current density equivalent to that of a conventional structure and thereby, prevents characteristics degradation at the time of operation.
    Type: Application
    Filed: March 14, 2018
    Publication date: October 4, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Shinichiro MATSUNAGA
  • Patent number: 9953961
    Abstract: A semiconductor device can reduce the number of bonding wires. The semiconductor device includes two or more semiconductor elements each of which has electrodes on a first main surface and a second main surface, an electrode plate that has one surface which is bonded to electrodes on the first main surfaces of the semiconductor elements, with a first bonding material layer interposed therebetween, and extends over the electrodes on the first main surfaces of the two or more semiconductor elements, and a conductive plate that includes a first lead terminal and a semiconductor element bonding portion which is bonded to electrodes on the second main surfaces of the semiconductor elements. A second bonding material layer is interposed therebetween, and is connected to the electrodes on the second main surfaces of the two or more semiconductor elements.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: April 24, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Yokoyama, Masaaki Ochiai, Atsushi Maruyama, Tomonori Seki, Shinichiro Matsunaga
  • Patent number: 9728599
    Abstract: An edge termination structure that surrounds an active region is disposed outside the active region. In the active region, a MOS gate structure is disposed. Inside an n?-type drift layer, an n-type CS region that becomes a minority carrier barrier is disposed in a surface layer on a p+-type base layer side. The n-type CS region is disposed in the active region and is not disposed in the edge termination structure. Thus, the impurity concentration of the n?-type drift layer inside the edge termination structure is low enough to enable high breakdown voltage to be realized. In the n?-type drift layer, which has a low impurity concentration, a JTE structure that is formed from first and second JTE regions is disposed.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: August 8, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shinichiro Matsunaga
  • Publication number: 20150028467
    Abstract: A semiconductor device can reduce the number of bonding wires. The semiconductor device includes two or more semiconductor elements each of which has electrodes on a first main surface and a second main surface, an electrode plate that has one surface which is bonded to electrodes on the first main surfaces of the semiconductor elements, with a first bonding material layer interposed therebetween, and extends over the electrodes on the first main surfaces of the two or more semiconductor elements, and a conductive plate that includes a first lead terminal and a semiconductor element bonding portion which is bonded to electrodes on the second main surfaces of the semiconductor elements. A second bonding material layer is interposed therebetween, and is connected to the electrodes on the second main surfaces of the two or more semiconductor elements.
    Type: Application
    Filed: October 10, 2014
    Publication date: January 29, 2015
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi YOKOYAMA, Masaaki OCHIAI, Atsushi MARUYAMA, Tomonori SEKI, Shinichiro MATSUNAGA
  • Patent number: 8921928
    Abstract: A semiconductor device having a low on resistance and high integration level with respect to the surface area of a substrate is provided. In the semiconductor device, a first trench, a second trench, and a third trench are provided in an element formation region provided on a semiconductor substrate. Metal is deposited within the first trench and second trench, to form a drain electrode and a source electrode, respectively. Polysilicon is deposited inside the third trench with a gate insulating film intervening, and a gate electrode is formed.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: December 30, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Shinichiro Matsunaga
  • Patent number: 8378418
    Abstract: A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: February 19, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Mutsumi Kitamura, Akio Sugi, Naoto Fujishima, Shinichiro Matsunaga
  • Patent number: 8034810
    Abstract: ?-Amino hydroxamic acid derivative of the formula I, in which R is C2-C7-alkyl, which is mono-, di- or trisubstituted by halogen, nitro, lower acyloxy, trifluoromethoxy, cyano, C3-C5-cycloalkyl or unsubstituted or substituted C3-C6-heteroaryl comprising one or two heteroatoms selected from the group consisting of O, S and N; or C3-C7-alkenyl or C3-C7-alkynyl, which in each case is unsubstituted or mono-, di- or trisubstituted by halogen, nitro, lower acyloxy, trifluoromethoxy, cyano, C3-C5-cycloalkyl or unsubstituted or substituted C3-C6-heteroaryl comprising one or two heteroatoms selected from the group consisting of O, S and N; and the other symbols are as defined in claim 1, are described. These compounds are MMP and in particular MMP2 inhibitors and can be used for treatment of MMP dependent diseases, in particular inflammation conditions, rheumatoid arthritis, osteoarthritis, tumors (tumor growth, metastasis, progression or invasion) and pulmonary disorders (e.g. emphysema, COPD).
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: October 11, 2011
    Assignee: Novartis AG
    Inventors: Werner Breitenstein, Kenji Hayakawa, Genji Iwasaki, Takanori Kanazawa, Tatsuhiko Kasaoka, Shinichi Koizumi, Shinichiro Matsunaga, Motowo Nakajima, Junichi Sakaki
  • Publication number: 20110204437
    Abstract: A semiconductor device having a low on resistance and high integration level with respect to the surface area of a substrate is provided. In the semiconductor device, a first trench, a second trench, and a third trench are provided in an element formation region provided on a semiconductor substrate. Metal is deposited within the first trench and second trench, to form a drain electrode and a source electrode, respectively. Polysilicon is deposited inside the third trench with a gate insulating film intervening, and a gate electrode is formed.
    Type: Application
    Filed: May 2, 2011
    Publication date: August 25, 2011
    Applicant: Fuji Electric Systems Co., Ltd.
    Inventor: Shinichiro MATSUNAGA
  • Publication number: 20100330398
    Abstract: A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.
    Type: Application
    Filed: August 26, 2010
    Publication date: December 30, 2010
    Applicant: Fuji Electric Systems Co., Ltd.
    Inventors: Mutsumi Kitamura, Akio Sugi, Naoto Fujishima, Shinichiro Matsunaga
  • Patent number: 7800167
    Abstract: A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: September 21, 2010
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Mutsumi Kitamura, Akio Sugi, Naoto Fujishima, Shinichiro Matsunaga
  • Patent number: 7737664
    Abstract: A battery protective device that protects against battery damage and semiconductor destruction from overdischarge and overcharge of the battery. Resistance across switching elements is controllable to prevent current leakage through parasitic dipole elements in the integrated circuit. Current is detected with an overdischarge detecting circuit and an overcharge detecting circuit. Direction of the current to/from the battery is detected by discharge overcurrent and charge overcurrent detecting circuits. Switching discharge FETs and charge FETs are enabled as independently controlled, ON-OFF parallel switching elements, interposed in series in the charge/discharge current path of the battery. Only a part of the discharge or charge switching FETs can be turned ON and OFF for accurate current control in accordance with the detected current and its direction.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: June 15, 2010
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventor: Shinichiro Matsunaga
  • Publication number: 20090085106
    Abstract: A semiconductor device having a low on resistance and high integration level with respect to the surface area of a substrate is provided. In the semiconductor device, a first trench, a second trench, and a third trench are provided in an element formation region provided on a semiconductor substrate. Metal is deposited within the first trench and second trench, to form a drain electrode and a source electrode, respectively. Polysilicon is deposited inside the third trench with a gate insulating film intervening, and a gate electrode is formed.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 2, 2009
    Applicant: Fuji Electric Device Technology Co., Ltd.
    Inventor: Shinichiro Matsunaga