Abstract: There is a problem that an area of a principal current cell is reduced by an area of a bonding pad wiring layer for a sub-cell. A source electrode 9b of a current detection cell 22 is electrically connected to a bonding pad wiring layer 12 formed on an interlayer insulating film 10 via a wiring layer contact 11. The bonding pad wiring layer 12 is formed with respect to a source electrode 9a of a principal current cell 21 so as to cover a part of the source electrode 9a via the interlayer insulating film 10. As a result, the source electrode 9b is miniaturized, and a size of the source electrode 9b is made substantially equal to a size of the current detection cell 22. Therefore, the current detection cell 22 and the principal current cell 21 are disposed close to each other.

Abstract: Provided is a power conversion device capable of observing a chip temperature with high accuracy without increasing a cost of the power conversion device mounted with a current sense element for observing a main current of a power device. A main control MOSFET 11, a current MOSFET 12, and a diode 13 connected to a source electrode 8 of the main control MOSFET 11 and a source electrode 9 of the current MOSFET 12 are mounted in a chip of a power device, a temperature measurement circuit 3 is connected to the source electrode 9 of the current MOSFET 12, and when the main control MOSFET 11 is in an off state, a forward current (If) is caused to flow through the diode 13, and an anode potential is observed to measure the chip temperature.

Abstract: An LDMOS transistor includes a P-type body region formed on a main surface of a semiconductor substrate, an N-type source region, an N-type drift region, an N-type drain region, a gate electrode formed via a gate insulating film, a first field plate formed on the drift region via a first insulating film, a plurality of second field plates being in contact with the source region or the gate electrode and formed on the first field plate via a second insulating film, a P-type first buried region, and a P-type second buried region having an impurity concentration lower than an impurity concentration of the first buried region. Distances of the first and second field plates from the drain region in the semiconductor substrate plane direction decrease toward the upper layers, and have a predetermined relationship with the distances between the first and second buried regions and the drain region.

Abstract: A power conversion apparatus accurately estimates a main current of a power device using observation of a sense current. The power conversion apparatus includes: an inverter circuit including a device having a main element and a sense element; a temporary-main-current estimator estimates a current flowing through the main element, from a sense current flowing through the sense element, as a temporary main current; a temperature-difference estimator configured to estimate a temperature difference between the main element and the sense element based on a gate drive signal for the main element and the temporary main current; a main-current corrector corrects the temporary main current using the estimated temperature difference and a temperature characteristic of on-resistance of the main element and output the corrected temporary main current as a corrected main current; and an inverter control circuit configured to output the gate drive signal based on the corrected main current.

Abstract: Provided are a semiconductor device having small characteristic variations with time and high reliability and an in-vehicle control device using the same, the semiconductor device including a plurality of transistor elements constituting a current mirror circuit or a differential amplifier circuit that requires high relative accuracy.

Abstract: There is a problem that an area of a principal current cell is reduced by an area of a bonding pad wiring layer for a sub-cell. A source electrode 9b of a current detection cell 22 is electrically connected to a bonding pad wiring layer 12 formed on an interlayer insulating film 10 via a wiring layer contact 11. The bonding pad wiring layer 12 is formed with respect to a source electrode 9a of a principal current cell 21 so as to cover a part of the source electrode 9a via the interlayer insulating film 10. As a result, the source electrode 9b is miniaturized, and a size of the source electrode 9b is made substantially equal to a size of the current detection cell 22. Therefore, the current detection cell 22 and the principal current cell 21 are disposed close to each other.

Abstract: Provided is a novel power conversion device that enables estimation of a temperature of a power device without using a temperature sensing diode and can accurately estimate a temperature and a current of a current sensing element that observes a main current. A measurement voltage (Vref) is applied between source terminals (31s and 49s) of a main control element 31 and a current sensing element 49 in a state in which the main control element 31 and the current sensing element 49 are turned off, and a temperature of a power device 30 is estimated from a current (Ib) flowing between the source terminals (31s and 49s) of the main control element 31 and the current sensing element 49 at the time of the application by using the fact that a resistance value of a semiconductor substrate between the source terminals of the main control element 31 and the current sensing element 49 has temperature dependency.

Abstract: An object is to provide a new electronic control unit that can improve detection accuracy of a sense current even in a region where the current value of the sense current is small. Provided is a sense current detection unit including a plurality of sense transistors that have different current flow rates and that are connected to current output transistors controlling a current flowing in a coil load. The current in the sense current detection unit is input to an analog/digital converter, and the current value of the current flowing in the sense current detection unit is converted into a digital value. The current value of the current flowing in the sense current detection unit is increased through a combination or a selection of the plurality of sense transistors of the sense current detection unit in a region where the current value of the main current of the current output transistors is small compared to a region where the current value of the main current is large.

Abstract: There is provided a high withstand voltage LDMOS field-effect transistor that enables the compatibility of an increase of its withstand voltage and a decrease of its ON resistance.

Abstract: Restraining a reduction in an electric current detection accuracy, which is due to the temperature difference between an output MOS transistor and a sense MOS transistor, and easing a limitation on the layout of the sense MOS transistor. A semiconductor device includes: an output MOS transistor that has an output transistor portion including a source, a gate, and a drain formed on a semiconductor chip, and outputs an electric current for driving an external load; and a sense MOS transistor that has a sense transistor portion including a source, a gate, and a drain formed on the semiconductor chip, and having a width equal to a transverse width of the output transistor portion, and that detects the electric current output from the output MOS transistor.

Abstract: Provided are a semiconductor device having small characteristic variations with time and high reliability and an in-vehicle control device using the same, the semiconductor device including a plurality of transistor elements constituting a current mirror circuit or a differential amplifier circuit that requires high relative accuracy.

Abstract: A semiconductor device obtains high current ratio accuracy by eliminating an influence of plasma charging using a MOS-type transistor in which a channel region is isolated and separated from a semiconductor substrate. In a current mirror circuit in which both of a well of a NMOS-type transistor that generates a bias and a well of a NMOS-type transistor that receives the bias are formed insulated and separated from a semiconductor substrate, a connection circuit is connected between gate electrodes and wells of NMOS-type transistors without through the semiconductor substrate, and the connection circuit makes the gate electrodes and the wells in an electrically short-circuited state during manufacturing of the current mirror circuit, and makes the gate electrodes and the wells in a disconnected state in at least one direction during a mounting operation.

Abstract: Provided is a vehicle-mounted semiconductor device enabling a temperature increase of active elements to be restricted. A vehicle-mounted semiconductor device includes: a semiconductor substrate; a plurality of active elements formed on the semiconductor substrate; a plurality of trenches surrounding the plurality of active elements to insulate and separate the active elements; and a terminal connecting in parallel the plurality of active elements insulated and separated by different trenches among the plurality of trenches and connected to an outside.

Abstract: A semiconductor device obtains high current ratio accuracy by eliminating an influence of plasma charging using a MOS-type transistor in which a channel region is isolated and separated from a semiconductor substrate. In a current mirror circuit in which both of a well of a NMOS-type transistor that generates a bias and a well of a NMOS-type transistor that receives the bias are formed insulated and separated from a semiconductor substrate, a connection circuit is connected between gate electrodes and wells of NMOS-type transistors without through the semiconductor substrate, and the connection circuit makes the gate electrodes and the wells in an electrically short-circuited state during manufacturing of the current mirror circuit, and makes the gate electrodes and the wells in a disconnected state in at least one direction during a mounting operation.

Abstract: A semiconductor device capable of enhancing uniformity of temperatures of transistors in an active clamp state while maintaining current performance is provided. A power transistor is connected to a power transistor in parallel. An active clamp circuit is provided in a path from a connection point between the power transistors to a gate of the power transistor and is conducted in a case where a voltage of the connection point exceeds a first threshold. An active clamp cutoff circuit is provided in a path from the active clamp circuit to a gate of the power transistor and cuts off or suppresses a current flowing into the path.

Abstract: Restraining a reduction in an electric current detection accuracy, which is due to the temperature difference between an output MOS transistor and a sense MOS transistor, and easing a limitation on the layout of the sense MOS transistor. A semiconductor device includes: an output MOS transistor that has an output transistor portion including a source, a gate, and a drain formed on a semiconductor chip, and outputs an electric current for driving an external load; and a sense MOS transistor that has a sense transistor portion including a source, a gate, and a drain formed on the semiconductor chip, and having a width equal to a transverse width of the output transistor portion, and that detects the electric current output from the output MOS transistor.

Abstract: An object is to provide a new electronic control unit that can improve detection accuracy of a sense current even in a region where the current value of the sense current is small. Provided is a sense current detection unit including a plurality of sense transistors that have different current flow rates and that are connected to current output transistors controlling a current flowing in a coil load. The current in the sense current detection unit is input to an analog/digital converter, and the current value of the current flowing in the sense current detection unit is converted into a digital value. The current value of the current flowing in the sense current detection unit is increased through a combination or a selection of the plurality of sense transistors of the sense current detection unit in a region where the current value of the main current of the current output transistors is small compared to a region where the current value of the main current is large.

Abstract: It is an object of the present invention to provide a switch element and a load driving apparatus capable of suppressing a characteristic change of an on-resistance without lowering an off-breakdown voltage. The switching element includes a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode. Alternatively, in the load driving apparatus including a current driving switch element and a current detecting switch element that is connected in parallel to the load driving switch element and that detects an energization current of the load driving switch element, the current detecting switch element includes at least a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode.

Abstract: To provide a semiconductor device capable of restricting the substrate bias effect of a high-side transistor while enhancing the heat radiation property of a low-side transistor. A high-side NMOS transistor 101 is formed in a region S1 on the surface of a SOI substrate 30. A trench 41 surrounds the high-side NMOS transistor 101. SiO2 (first insulator) embeds the trench 41. A low-side NMOS transistor 102 is formed in a region S2 on the surface of the SOI substrate 30 around the trench 41. The side face Sf connecting the region S2 forming the low-side NMOS transistor 102 therein and the backside of the SOI substrate 30 is exposed.

Abstract: A semiconductor device capable of enhancing uniformity of temperatures of transistors in an active clamp state while maintaining current performance is provided. A power transistor is connected to a power transistor in parallel. An active clamp circuit is provided in a path from a connection point between the power transistors to a gate of the power transistor and is conducted in a case where a voltage of the connection point exceeds a first threshold. An active clamp cutoff circuit is provided in a path from the active clamp circuit to a gate of the power transistor and cuts off or suppresses a current flowing into the path.