Patents by Inventor Shinji Nakazato
Shinji Nakazato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916531Abstract: An acoustic wave device includes a support substrate, a piezoelectric layer provided over the support substrate, comb-shaped electrodes disposed on the piezoelectric layer, each of the comb-shaped electrodes including electrode fingers exciting an acoustic wave, a temperature compensation film interposed between the support substrate and the piezoelectric layer and having a temperature coefficient of an elastic constant opposite in sign to that of the piezoelectric layer, a boundary layer interposed between the support substrate and the temperature compensation film, an acoustic velocity of a bulk wave propagating through the boundary layer being higher than an acoustic velocity of a bulk wave propagating through the temperature compensation film and being lower than an acoustic velocity of a bulk wave propagating through the support substrate, and an intermediate layer interposed between the support substrate and the boundary layer and having a Q factor less than a Q factor of the boundary layer.Type: GrantFiled: June 30, 2021Date of Patent: February 27, 2024Assignee: TAIYO YUDEN CO., LTD.Inventors: Toshiharu Nakazato, Shinji Yamamoto, Ryouta Iwabuchi, Naoki Takahashi
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Patent number: 7982314Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: GrantFiled: July 21, 2010Date of Patent: July 19, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Publication number: 20100308458Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: ApplicationFiled: July 21, 2010Publication date: December 9, 2010Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Patent number: 7808107Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: GrantFiled: May 8, 2009Date of Patent: October 5, 2010Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Publication number: 20090219069Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: ApplicationFiled: May 8, 2009Publication date: September 3, 2009Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Patent number: 7547971Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: GrantFiled: August 12, 2005Date of Patent: June 16, 2009Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Publication number: 20060006480Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: ApplicationFiled: August 12, 2005Publication date: January 12, 2006Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Patent number: 6963136Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: GrantFiled: December 17, 2001Date of Patent: November 8, 2005Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Patent number: 6864559Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: GrantFiled: March 4, 2003Date of Patent: March 8, 2005Assignee: Renesas Technology Corp.Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Patent number: 6740958Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: GrantFiled: April 4, 2002Date of Patent: May 25, 2004Assignee: Renesas Technology Corp.Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Publication number: 20040007778Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: ApplicationFiled: June 19, 2003Publication date: January 15, 2004Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Publication number: 20030178699Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: ApplicationFiled: March 4, 2003Publication date: September 25, 2003Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Publication number: 20020153591Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: ApplicationFiled: April 4, 2002Publication date: October 24, 2002Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Patent number: 6208010Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: GrantFiled: December 18, 1995Date of Patent: March 27, 2001Assignee: Hitachi, Ltd.Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Patent number: 5638335Abstract: A memory device comprising a memory array having a plurality of bits, including parity bits, and comprising a plurality of memory blocks, and a bit structure changing section for changing the input/output bits of the memory array, wherein the number of the memory blocks are prescribed to be an integral multiple of three and the input/output bits of the plurality of memory blocks are even. Thereby, the bit structure of the semiconductor memory, having parity bits and which is capable of changing the input/output bits to a plurality of bit structures, can be changed while maintaining the bit structure of the memory blocks even and without increase in propagation delay time.Type: GrantFiled: May 17, 1996Date of Patent: June 10, 1997Assignee: Hitachi, Ltd.Inventors: Noboru Akiyama, Seigoh Yukutake, Sadayuki Ohkuma, Akihiko Emori, Takashi Akioka, Shuichi Miyaoka, Shinji Nakazato, Kinya Mitsumoto
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Patent number: 5497023Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: GrantFiled: December 8, 1994Date of Patent: March 5, 1996Assignee: Hitachi, Ltd.Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikasu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Patent number: 5386135Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: GrantFiled: April 12, 1994Date of Patent: January 31, 1995Assignee: Hitachi, Ltd.Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Patent number: 5324982Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: GrantFiled: October 2, 1991Date of Patent: June 28, 1994Assignee: Hitachi, Ltd.Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Patent number: 5148255Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.Type: GrantFiled: January 23, 1991Date of Patent: September 15, 1992Assignee: Hitachi, Ltd.Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
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Patent number: 5050127Abstract: A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.Type: GrantFiled: October 19, 1989Date of Patent: September 17, 1991Assignee: Hitachi, Ltd.Inventors: Kinya Mitsumoto, Shinji Nakazato, Yoshiaki Yazawa, Masanori Odaka, Hideaki Uchida, Nobuaki Miyakawa