Abstract: The processing apparatus in the present invention is a processing apparatus which executes a program and performs processes of the program, and includes the following: an execution circuit having a plurality of operation modes, each of which has a different effect on the processing performance and the power consumption of the processing apparatus; a measurement unit operable to measure at least one of a process execution performance and an execution power consumption of the processor circuit; and a control unit operable to compare a target value and a measurement result from the measurement unit, and to switch the operation modes in accordance to a result of the comparison.

Abstract: A virtual multiprocessor system which does not require a memory apparatus for debugging includes: a physical processor, storage units for storing status information indicating respective statuses of logic processors, a dispatch unit which assigns one of the logic processors by switching the logic processors with respect to a physical processor, and an interrupt unit which suspends the processing currently executed by a current logic processor among the logic processors by issuing a debug interrupt request to the current logic processor; in the virtual multiprocessor system, the dispatch unit stores status information corresponding to the current logic processor into one of the storage units in response to the debug interrupt request issued to the current logic processor that is assigned to the physical processor.

Abstract: The present invention provides an operational processing apparatus which can guarantee a period for executing instructions in the shortest cycle when the operational processing apparatus synchronizes with a hardware accelerator. A processor in the present invention simultaneously issues and executes instructions including instruction groups having a simultaneously issueable instruction. The processor executes a program including a specific instruction. The specific instruction instructs to exclude an instruction subsequent to the specific instruction out of the instruction groups including the specific instruction, and to suspend issuing the instruction subsequent to the specific instruction only during a predetermined period immediately after the specific instruction is issued.

Abstract: A processing apparatus which executes a program and performs processes of the program, includes an execution circuit including a plurality of central processing units, each having a respective cache memory, and each of the respective cache memories has an N-way set-associative structure with N-ways in which one line is made up of plural words. Each of the respective cache memories includes a data memory array which is simultaneously read-out in multiple-word-widths, and can be read-out using one of a type one read-out and a type two read-out. In the type one read-out, plural words in the same word positions within respective lines are simultaneously read-out from corresponding lines belonging to different ways, and in the type two read out, plural words making up one line of one way are simultaneously read-out. The cache memory has a first read-out mode and a second read-out mode.

Abstract: Provided is a multithreaded processor that can accurately estimate processing time necessary for each thread, and a multithreaded processor that simultaneously executes instruction streams, the multithreaded processor including: a computing unit group that executes instructions; an instruction scheduler that groups the instructions into groups for each of the instruction streams, the instructions being included in the each of instruction streams, and each of the groups being made up of instructions among the instructions to be simultaneously issued to the computing units; an instruction buffer which holds the instructions for each of the groups grouped by the instruction scheduler, the instructions being included in the each of instruction streams; and an issued instruction determining unit that reads the instructions for each of the groups from the instruction buffer in each of execution cycles of the multithreaded processor, and that issues the read instructions to the computing unit group.

Abstract: A cache access transmission means outputs an access address, obtained from a CPU by way of a local cache access address input means, to a shared address bus via a remote cache access address output means. A cache access control means accesses a cache memory by using the access address obtained from the shared address bus by way of a remote cache access address input means. That is, an access address output from a CPU of a first processor is output from the cache access transmission means and received by the cache access control means so as to be used in accessing a cache memory in a second processor.

Abstract: A scan test circuit is provided with a scan chain having n pieces of scan storage elements (n: integer, n>1); a scan clock generation circuit which is able to control a frequency of a first clock to be used for shifting data into the first to (n?1)th scan storage elements, and a frequency of a second clock to be used for shifting data into the n-th scan storage element and performing actual operation, independently from each other; and a scan selection internal signal generation circuit for generating a scan selection internal signal that is synchronized with the second clock.

Abstract: An electric current sensor includes: a core having a ring shape and including a plurality of core pieces, which are laminated and integrated to provide the core; a magnetic gap disposed on a predetermined part of the core; a Hall element disposed in the magnetic gap; a body for accommodating the core and the Hall element; and a seal member for sealing the core and the Hall element into the body. Each core piece has a thin plate shape, and the core includes deformation preventing means for preventing a deformation of the magnetic gap.

Abstract: The processing apparatus in the present invention is a processing apparatus which executes a program and performs processes of the program, and includes the following: an execution circuit having a plurality of operation modes, each of which has a different effect on the processing performance and the power consumption of the processing apparatus; a measurement unit operable to measure at least one of a process execution performance and an execution power consumption of the processor circuit; and a control unit operable to compare a target value and a measurement result from the measurement unit, and to switch the operation modes in accordance to a result of the comparison.

Abstract: An electric current sensor includes: a core having a ring shape and including a plurality of core pieces, which are laminated and integrated to provide the core; a magnetic gap disposed on a predetermined part of the core; a Hall element disposed in the magnetic gap; a body for accommodating the core and the Hall element; and a seal member for sealing the core and the Hall element into the body. Each core piece has a thin plate shape, and the core includes deformation preventing means for preventing a deformation of the magnetic gap.

Abstract: A stored data modifier modifies data starting at any arbitrary address on a storage medium that should output a data word with a multi-byte width. A masked ROM outputs a 2N-byte data word starting at an address specified as a multiple of 2N by an address signal. A correspondence detector determines whether or not correspondence is found between a correction address and one of a number 2N of addresses starting at, or preceding, the address specified by the address signal. If the correspondence detector has found the correspondence, a stored data selecting section selectively outputs, on a byte-by-byte basis, either the output of the masked ROM or correction data in accordance with the address signal and the correction address.

Abstract: A scan test circuit is provided with a scan chain having n pieces of scan storage elements (n: integer, n>1); a scan clock generation circuit which is able to control a frequency of a first clock to be used for shifting data into the first to (n>1)th scan storage elements, and a frequency of a second clock to be used for shifting data into the n-th scan storage element and performing actual operation, independently from each other; and a scan selection internal signal generation circuit for generating a scan selection internal signal that is synchronized with the second clock.

Abstract: A processor that accesses a plurality of regions allocated to memory includes: a judging unit for judging which region is accessed based on an access address; an assuming unit for assuming which region is accessed based on the access address, the assuming unit producing an assumption result faster than the judging unit produces a judgement result; an accessing unit for starting access based on the assumption result; a detecting unit for detecting a disagreement between the judgement result and the assumption result; and a control unit for stopping the access that has been started if the detecting unit has detected the disagreement, and controlling the accessing unit to perform another access based on the judgement result.

Abstract: A stored data modifier modifies data starting at any arbitrary address on a storage medium that should output a data word with a multi-byte width. A masked ROM outputs a 2N-byte data word starting at an address specified as a multiple of 2N by an address signal. A correspondence detector determines whether or not correspondence is found between a correction address and one of a number 2N of addresses starting at, or preceding, the address specified by the address signal. If the correspondence detector has found the correspondence, a stored data selecting section selectively outputs, on a byte-by-byte basis, either the output of the masked ROM or correction data in accordance with the address signal and the correction address.

Abstract: A processor executes a program loop at high speed using a branch target information register instruction which is set immediately before the program loop and a high-speed loop instruction which is set at an end of the program loop. When the branch target information register instruction is decoded by an instruction decoder, code in a fetched instruction buffer is sent to a branch target instruction register, and a shifted pointer in a decoded instruction counter is sent to a branch target fetch address register. After the high-speed loop instruction has been decoded by the instruction decoder and a branch condition is satisfied, the pointer in the branch target fetch address register is sent to a fetched instruction counter and to the decoded instruction counter while the code in the branch target instruction register is sent to a decoded instruction buffer. By using the shifted pointer in the decoded instruction counter, the high-speed loop instruction can be efficiently executed with small-scale hardware.

Abstract: A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two operands, respectively read out from the register and another register in the register set, should be added are pipeline-processed. In a high-speed mode in which an operation clock having a higher frequency is supplied, a data cache intervened between an instruction execution circuit and the data memory is controlled to supply a data word to a WB (write back) stage of the instruction execution circuit within two cycles with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is supplied from the WB stage to an EX (operation execution) stage of the instruction execution circuit.

Abstract: A CPU (central processing unit) including an instruction processor and a data processor is connected with a ROM (read only memory) bus, a RAM (random access memory) bus, and an IO (input-output) bus for inputting/outputting data independently of the ROM and RAM buses. A rewritable register included in a memory access controller stores a set value of the number of wait cycles in an access to a ROM, a set value of the number of wait cycles in an access to a RAM, and a set value for switching an input path in the data processor. These set values can be varied according to a cycle time of a CPU clock signal. In accordance with these set values, insertion of wait cycles in the instruction processor and the data processor is controlled, and it is determined whether or not an input of the data processor is latched.

Abstract: In a control signal detection method, a calibration error value is obtained by obtaining the mean value of the received continuous (4.times.n) data, and the calibration error is compensated with respect to the received data by subtracting the obtained calibration error value from the received data, and the correlation value is obtained on the basis of the corrected received data, so that the control signal is detected. Therefore, it is able to compensate the calibration error with ease and to detect the control signal efficiently, with a simple construction.

Abstract: An instruction address that is referred to by a microprocessor unit is inputted over an instruction address bus and is stored. While counting the number of times a clock is fed to the microprocessor unit, a comparison is made between the stored instruction address and an instruction address that the microprocessor provides onto the instruction address bus. A clock count value, obtained at the time when the aforesaid instruction addresses agree, is stored. If a stored instruction address and an instruction address on the instruction address bus agree for every stored clock count value, then the microprocessor is judged to repeatedly execute a sequence of instructions and the loop count value is incremented by one. When the loop count value exceeds a predetermined value, the microprocessor is judged to be placed in an idle state and the clock frequency is lowered.

Abstract: A semiconductor integrated circuit includes a functional block realizing at least part of a function of the semiconductor integrated circuit. The functional block includes a plurality of basic cells and a plurality of terminal cells. Each of the plurality of terminal cells has a connector for mediating a communication between another semiconductor integrated circuit and one of the plurality of basic cells.