Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.

Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.

Abstract: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.

Abstract: A semiconductor integrated circuit device includes first and second select gate electrodes that are sidewall-shaped along sidewalls of a memory gate structure. With this configuration, the memory gate structure is not disposed on the first select gate electrode and the second select gate electrode. Accordingly, the memory gate structure the first select gate structure, and the second select gate structure can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer on the first select gate electrode and a silicide layer on the second select gate electrode can be separated farther from a memory gate electrode by the thickness of a cap film. Accordingly, the silicide layers on the first select gate electrode and the second select gate electrode are unlikely to contact with the memory gate electrode, thereby preventing a short-circuit defect of the memory gate electrode.

Abstract: Disclosed herein is a wafer processing method including the steps of attaching a dicing tape to the back side of a wafer, the dicing tape being composed of a base tape, a DAF, and an adhesive layer for uniting the base tape and the DAF, imaging the wafer through the dicing tape to obtain an image of the wafer, detecting the positions of poor adhesion of the DAF from the image, storing the positions of poor adhesion detected above, dividing the wafer and the DAF into individual chips each having the DAF, curing the adhesive layer of the dicing tape by the application of ultraviolet light, selectively separating the chips with the DAF well adhered, at the boundary between the adhesive layer and the DAF according to the positions of poor adhesion stored above, and then picking up the chips with the DAF well adhered.

Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.

Abstract: A semiconductor light emitting device includes: a nitride semiconductor light emitting element including a nitride semiconductor substrate having a polar or semipolar surface and a nitride semiconductor multilayer film stacked on the polar or semipolar surface; and a mounting section to which the element is mounted. The nitride semiconductor multilayer film includes an electron block layer. The electron block layer has a smaller lattice constant than the nitride semiconductor substrate. The mounting section includes at least a first mounting section base. The first mounting section base is located close to the nitride semiconductor light emitting element. The first mounting section base has a lower thermal expansion coefficient than the nitride semiconductor multilayer film. The first mounting section base has a lower thermal conductivity than the nitride semiconductor multilayer film.

Abstract: Disclosed herein is a wafer processing method including the steps of attaching a dicing tape to the back side of a wafer, the dicing tape being composed of a base tape, a DAF, and an adhesive layer for uniting the base tape and the DAF, imaging the wafer through the dicing tape to obtain an image of the wafer, detecting the positions of poor adhesion of the DAF from the image, storing the positions of poor adhesion detected above, dividing the wafer and the DAF into individual chips each having the DAF, curing the adhesive layer of the dicing tape by the application of ultraviolet light, selectively separating the chips with the DAF well adhered, at the boundary between the adhesive layer and the DAF according to the positions of poor adhesion stored above, and then picking up the chips with the DAF well adhered.

Abstract: A grinding method includes a pre-grinding step of grinding a plate-shaped workpiece to a thickness just before a finish thickness is reached using a finish grinding unit, a thickness measuring step of measuring a thickness of the workpiece after the pre-grinding step, a calculation step of calculating, from the measured thickness of the workpiece, a variation amount of the distance between a holding face of the chuck table and a grinding face of a finish grindstone before and after inclination adjustment of the chuck table, and a height adjustment step of adjusting, on the basis of the variation amount, the inclination of the chuck table while adjusting the height of the finish grinding unit so that the relative moving speed between the finish grindstone and the workpiece in a state in which the grinding face contacts with an upper face of the workpiece becomes equal to zero.

Abstract: A grinding method includes a pre-grinding step of grinding a plate-shaped workpiece to a thickness just before a finish thickness is reached using a finish grinding unit, a thickness measuring step of measuring a thickness of the workpiece after the pre-grinding step, a calculation step of calculating, from the measured thickness of the workpiece, a variation amount of the distance between a holding face of the chuck table and a grinding face of a finish grindstone before and after inclination adjustment of the chuck table, and a height adjustment step of adjusting, on the basis of the variation amount, the inclination of the chuck table while adjusting the height of the finish grinding unit so that the relative moving speed between the finish grindstone and the workpiece in a state in which the grinding face contacts with an upper face of the workpiece becomes equal to zero.

Abstract: A semiconductor light emitting device includes: a nitride semiconductor light emitting element including a nitride semiconductor substrate having a polar or semipolar surface and a nitride semiconductor multilayer film stacked on the polar or semipolar surface; and a mounting section to which the element is mounted. The nitride semiconductor multilayer film includes an electron block layer. The electron block layer has a smaller lattice constant than the nitride semiconductor substrate. The mounting section includes at least a first mounting section base. The first mounting section base is located close to the nitride semiconductor light emitting element. The first mounting section base has a lower thermal expansion coefficient than the nitride semiconductor multilayer film. The first mounting section base has a lower thermal conductivity than the nitride semiconductor multilayer film.

Abstract: A semiconductor light emitting device includes: a nitride semiconductor light emitting element including a nitride semiconductor substrate having a polar or semipolar surface and a nitride semiconductor multilayer film stacked on the polar or semipolar surface; and a mounting section to which the element is mounted. The nitride semiconductor multilayer film includes an electron block layer. The electron block layer has a smaller lattice constant than the nitride semiconductor substrate. The mounting section includes at least a first mounting section base. The first mounting section base is located close to the nitride semiconductor light emitting element. The first mounting section base has a lower thermal expansion coefficient than the nitride semiconductor multilayer film. The first mounting section base has a lower thermal conductivity than the nitride semiconductor multilayer film.

Abstract: Provided is a highly reliable nitride semiconductor laser element having a robust end face protection film not being peeled even in laser operation. The nitride semiconductor laser element includes: a semiconductor multi-layer structure including a group III nitride semiconductor and having a light-emitting end face; and a protection film including a dielectric multi-layer film and covering the light-emitting end face of the semiconductor multi-layer structure. The protection film includes an end face protection layer and an oxygen diffusion suppression layer arranged sequentially in stated order from the light-emitting end face. The end face protection layer includes a crystalline film comprising nitride including aluminum. The oxygen diffusion suppression layer has a structure in which a metal oxide film is between silicon oxide films. The metal oxide film is crystallized by laser light.

Abstract: A semiconductor light-emitting device includes a first heat sink and a second heat sink both formed of an insulating member and facing and thermally connected to each other, and a semiconductor light-emitting element. The semiconductor light-emitting element is held in a cavity between the first heat sink and the second heat sink. The second heat sink has a first electrode and a second electrode on a surface facing the first heat sink, and a third electrode and a fourth electrode on a surface opposite to the surface facing the first heat sink. The first electrode is connected to a lower electrode of the light-emitting element. The second electrode is connected to an upper electrode of the light-emitting element. The first electrode and the third electrode are connected to each other, and the second electrode and the fourth electrode are connected to each other.

Abstract: A nitride semiconductor light-emitting element includes a layered semiconductor body which is made of a group III nitride semiconductor, and includes a light-emitting facet, and a multilayer protective film which is formed to cover the light-emitting facet of the layered semiconductor body, and includes a plurality of insulating films. The multilayer protective film includes a first protective film and a second protective film covering the first protective film. The first protective film is a crystalline film which is made of nitride containing aluminum, and is at least partially crystallized. The second protective film is a crystalline film which is made of oxide containing aluminum, and is at least partially crystallized.

Abstract: A nitride semiconductor light-emitting system includes a nitride semiconductor light-emitting device, a base mount holding the nitride semiconductor light-emitting device, having an opening, and containing first metal as a main component, a cap adhered to the base mount, and a lead pin penetrating the opening. The lead pin is fixed to an inner wall of the opening with an insulating member and a buffer member interposed therebetween, the buffer member and the insulating member being stacked on the inner wall in this order. The insulating member contains silicon oxide as a component. The buffer member is made of second metal having a smaller standard oxidation-reduction potential than the first metal, or an alloy containing the second metal.

Abstract: The present invention provides a urethane foam molded product that has high thermal conductivity with minimal change to its physical properties. A simple method for producing the same is also provided. The urethane foam molded product includes a base material formed of a polyurethane foam, and a thermal conductive filler mixed in the base material and oriented to form mutual connections. The thermal conductive filler is formed of composite particles that include thermal conductive particles formed of a nonmagnetic material, and magnetic particles adhered to the surfaces of the thermal conductive particles.

Abstract: Provided is a highly reliable nitride semiconductor laser element having a robust end face protection film not being peeled even in laser operation. The nitride semiconductor laser element includes: a semiconductor multi-layer structure including a group III nitride semiconductor and having a light-emitting end face; and a protection film including a dielectric multi-layer film and covering the light-emitting end face of the semiconductor multi-layer structure. The protection film includes an end face protection layer and an oxygen diffusion suppression layer arranged sequentially in stated order from the light-emitting end face. The end face protection layer includes a crystalline film comprising nitride including aluminum. The oxygen diffusion suppression layer has a structure in which a metal oxide film is between silicon oxide films. The metal oxide film is crystallized by laser light.

Abstract: A semiconductor light emitting device includes: a nitride semiconductor light emitting element including a nitride semiconductor substrate having a polar or semipolar surface and a nitride semiconductor multilayer film stacked on the polar or semipolar surface; and a mounting section to which the element is mounted. The nitride semiconductor multilayer film includes an electron block layer. The electron block layer has a smaller lattice constant than the nitride semiconductor substrate. The mounting section includes at least a first mounting section base. The first mounting section base is located close to the nitride semiconductor light emitting element. The first mounting section base has a lower thermal expansion coefficient than the nitride semiconductor multilayer film. The first mounting section base has a lower thermal conductivity than the nitride semiconductor multilayer film.

Abstract: A nitride semiconductor light emitting device includes a nitride semiconductor light emitting element and a package in which the nitride semiconductor light emitting element is accommodated. The package includes a base table in which openings are formed, a cap defining an accommodation space for accommodating the nitride semiconductor light emitting element together with the base table, lead pins passing through the openings and electrically connected to the nitride semiconductor light emitting element, and insulating members embedded in the openings to insulate the base table from the lead pins. At least parts of the insulating members which are located on an accommodation space side are made of a first insulating material containing no Si—O bond.