Abstract: A protocol chip stores requests from a computer in a port queue, on the basis of an index indicating a slot of the port queue which allows subsequent storing. MPs each hold a CI of the slot having undergone a preceding search of the port queue by the MP, search this port queue from the slot that the pointer indicates, search for a request addressed to a logical device to which the MP corresponds, and store this request in a virtual queue corresponding to the logical device, to process the request.

Abstract: A protocol chip stores requests from a computer in a port queue, on the basis of an index indicating a slot of the port queue which allows subsequent storing. MPs each hold a CI of the slot having undergone a preceding search of the port queue by the MP, search this port queue from the slot that the pointer indicates, search for a request addressed to a logical device to which the MP corresponds, and store this request in a virtual queue corresponding to the logical device, to process the request.

Abstract: A storage control apparatus of the present invention controls the number of multiple commands issued from a host machine without shutting down the host machine. A communication port of the storage control apparatus carries out communications with the hosts in accordance with the iSCSI protocol. Command processing resources are managed for each communication port. A resource allocation control part calculates the number of commands capable of being received on the basis of the remaining amount of command processing resources inside shared port resources, a change in the number of commands received from a host, communication delay time, and the state of execution of a command issued from a host or the like. A MaxCmdSN is calculated by adding the results of command processing by a command execution part and the receivable number calculated by the resource allocation control part to the value of the latest CmdSN received from a host.

Abstract: There is provided a command multiplex number monitoring control scheme capable of avoiding issue of a QF status and getting rid of system performance degradation without adding command processing resources. Command issue multiplex numbers CMs (32, 16 and 8) for WWN1-LU2, WWN2-LU1 and WWN3-LU0 are set in a port PT1 so as to be associated with the host bus adaptors HBAs in higher rank apparatuses HOST-1, HOST-2 and HOST-3. Denoting the sum total of command issue multiplex numbers CMs for respective set access permissions by (C), an access permission satisfying the relationship represented as “command processing multiplex limit number (B)?the sum total (C) of command issue multiplex numbers CMs for respective access permissions” is not permitted. Thus, the command issue multiplex numbers of the connected higher rank apparatuses are monitored.

Abstract: A storage control system has a host computer having one or more initiators; a storage controller having one or more targets and storage areas, and also having a security property for defining access relationships between the targets and the storage areas; and a management module for storing access correspondence relationships between the initiators and the targets. When the security property is set in the storage controller, the storage controller sets the access correspondence relationships in the management module based on the security property.

Abstract: A storage control apparatus of the present invention controls the number of multiple commands issued from a host machine without shutting down the host machine. A communication port of the storage control apparatus carries out communications with the hosts in accordance with the iSCSI protocol. Command processing resources are managed for each communication port. A resource allocation control part calculates the number of commands capable of being received on the basis of the remaining amount of command processing resources inside shared port resources, a change in the number of commands received from a host, communication delay time, and the state of execution of a command issued from a host or the like. A MaxCmdSN is calculated by adding the results of command processing by a command execution part and the receivable number calculated by the resource allocation control part to the value of the latest CmdSN received from a host.

Abstract: A storage control system has a host computer having one or more initiators; a storage controller having one or more targets and storage areas, and also having a security property for defining access relationships between the targets and the storage areas; and a management module for storing access correspondence relationships between the initiators and the targets. When the security property is set in the storage controller, the storage controller sets the access correspondence relationships in the management module based on the security property.

Abstract: There is provided a command multiplex number monitoring control scheme capable of avoiding issue of a QF status and getting rid of system performance degradation without adding command processing resources. Command issue multiplex numbers CMs (32, 16 and 8) for WWN1-LU2, WWN2-LU1 and WWN3-LU0 are set in a port PT1 so as to be associated with the host bus adaptors HBAs in higher rank apparatuses HOST-1, HOST-2 and HOST-3. Denoting the sum total of command issue multiplex numbers CMs for respective set access permissions by (C), an access permission satisfying the relationship represented as “command processing multiplex limit number (B)?the sum total (C) of command issue multiplex numbers CMs for respective access permissions” is not permitted. Thus, the command issue multiplex numbers of the connected higher rank apparatuses are monitored.

Abstract: There is provided a command multiplex number monitoring control scheme capable of avoiding issue of a QF status and getting rid of system performance degradation without adding command processing resources. Command issue multiplex numbers CMs (32, 16 and 8) for WWN1-LU2, WWN2-LU1 and WWN3-LU0 are set in a port PT1 so as to be associated with the host bus adaptors HBAs in higher rank apparatuses HOST-1, HOST-2 and HOST-3. Denoting the sum total of command issue multiplex numbers CMs for respective set access permissions by (C), an access permission satisfying the relationship represented as “command processing multiplex limit number (B)?the sum total (C) of command issue multiplex numbers CMs for respective access permissions” is not permitted. Thus, the command issue multiplex numbers of the connected higher rank apparatuses are monitored.

Abstract: There is provided a command multiplex number monitoring control scheme capable of avoiding issue of a QF status and getting rid of system performance degradation without adding command processing resources. Command issue multiplex numbers CMs (32, 16 and 8) for WWN1-LU2, WWN2-LU1 and WWN3-LU0 are set in a port PT1 so as to be associated with the host bus adaptors HBAs in higher rank apparatuses HOST-1, HOST-2 and HOST-3. Denoting the sum total of command issue multiplex numbers CMs for respective set access permissions by (C), an access permission satisfying the relationship represented as “command processing multiplex limit number (B)?the sum total (C) of command issue multiplex numbers CMs for respective access permissions” is not permitted. Thus, the command issue multiplex numbers of the connected higher rank apparatuses are monitored.

Abstract: A data transfer control system in a data transfer apparatus including a plurality of data processing units having different data transfer speeds and a temporary holding circuit provided between the data processing units for temporarily holding data transferred between the data processing units. The data transfer apparatus sends a transfer request for data corresponding to a data storage capacity of the temporary holding circuit of the data transfer apparatus to the data processing unit on the side of sending data and sends a transfer request for data corresponding to the data storage capacity of the temporary holding circuit after an elapse of a delivering time of data to an information processing unit on the data transferred side of the temporary holding circuit from the time the data transfer request is sent until the requested data from the data processing unit on the data sending side reaches the temporary holding circuit of the data transfer apparatus.

Abstract: A data transfer control system in a data transfer apparatus including a plurality of data processing units having different data transfer speeds and a temporary holding circuit provided between the data processing units for temporarily holding data transferred between the data processing units. The data transfer apparatus sends a transfer request for data corresponding to a data storage capacity of the temporary holding circuit of the data transfer apparatus to the data processing unit on the side of sending data and sends a transfer request for data corresponding to the data storage capacity of the temporary holding circuit after an elapse of a delivering time of data to an information processing unit on the data transferred side of the temporary holding circuit from the time of the data transfer request is sent until the requested data from the data processing unit on the data sending side reaches the temporary holding circuit of the data transfer apparatus.