Abstract: A semiconductor device, including: first to fourth semiconductor regions, the fourth semiconductor region containing a first-conductivity-type impurity having a higher concentration than the first semiconductor region; first and second trenches; a gate electrode provided in the first trench; a Schottky electrode formed at an inner wall of the second trench, and in contact with the fourth semiconductor region; and a first electrode embedded in the second trench and in contact with the Schottky electrode. The fourth semiconductor region includes: an SBD portion formed at a sidewall of the second trench and in contact with the Schottky electrode, and an upper JFET portion provided between a sidewall of the first trench and the SBD portion. A junction between surfaces of the Schottky electrode and the SBD portion forms an SBD. A carrier concentration of the SBD portion is lower than the concentration of the first-conductivity-type impurity in the upper JFET portion.

Abstract: A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type and having a doping concentration lower than a doping concentration of the silicon carbide semiconductor substrate, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, trenches, first base regions, second base regions of the second conductivity type, and a co-doped region doped with aluminum and nitrogen. The co-doped region is provided in the first semiconductor layer, including regions between the first base regions and the second base regions and a layer that is closer to the silicon carbide semiconductor substrate than are the first base regions and the second base regions. The co-doped region has a carrier lifetime of not more than 0.01 ?s.

Abstract: A superjunction silicon carbide semiconductor device has a silicon carbide semiconductor substrate, a first semiconductor layer of the first conductivity type, a parallel pn region with first column regions of the first conductivity type and second column regions of a second conductivity type disposed therein repeatedly alternating with one another, a second semiconductor layer of the first conductivity type, a third semiconductor layer of the second conductivity type, a first semiconductor region of the first conductivity type, trenches, a second semiconductor region of the second conductivity type, a third semiconductor region of the second conductivity type, gate electrodes, and an electrode. The first column regions and the second column regions contain phosphorus as a dopant.

Abstract: A semiconductor device capable of suppressing forward voltage degradation and loss during turn-on. A vertical MOSFET includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, third semiconductor regions of the second conductivity type, first trenches and second trenches, gate electrodes provided in the first trenches via a gate insulating film, and Schottky metal provided in the second trenches. In a region between an active region through which current flows during an on-state and an edge region that surrounds a periphery of the active region and sustains a breakdown voltage, sidewalls of the second trenches are apart from the second semiconductor regions and the third semiconductor regions.

Abstract: A destructive breakdown mode that leads to the destruction of a device is suppressed, in the case where a gallium nitride-based high electron mobility transistor is used as a power device. A diode is connected in antiparallel to a HEMT, and this antiparallel connected diode is designed such that an avalanche breakdown occurs therein before the drain-source voltage, which is the difference between the drain potential applied to a drain electrode and the source potential applied to a source electrode, exceeds the withstand voltage of the HEMT.

Abstract: According to an embodiment, an electrode group is provided. The electrode group includes a positive electrode, and a negative electrode. The negative electrode active material-containing layer includes a facing section which faces the positive electrode active material-containing layer and a non-facing section which does not. A first fluorine-containing coating is formed on a main surface of the negative electrode active material-containing layer in at least a part of the non-facing section. The abundance ratio of fluorine atoms included in the first fluorine-containing coating is in the range of 2.5 atom % to 10 atom %.

Abstract: At a front surface of a silicon carbide base, an n?-type drift layer, a p-type base layer, a first n+-type source region, a second n+-type source region, and a trench that penetrates the first and the second n+-type source regions and the p-type base layer and reaches the n-type region are provided. In the trench, the gate electrode is provided via a gate insulating film, an interlayer insulating film is provided in the trench on the gate electrode, and a barrier metal is provided in the trench on the interlayer insulating film.

Abstract: A semiconductor device, including: a drift layer of a first conductivity type provided in a semiconductor base; a base layer of a second conductivity type provided in the semiconductor base at a front surface side thereof; a plurality of first trenches provided in the semiconductor base at a front surface side thereof, and having a plurality of first portions extending in a first direction to form a striped pattern; a second trench provided in the semiconductor base at a front surface side thereof, and having a plurality of second portions extending parallel to the first portions; a plurality of gate electrodes respectively provided in the first trenches; and a diode electrode provided in the second trench. The diode electrode includes: a plurality of inner electrodes provided in the second portions, and an outer electrode connecting the inner electrodes and surrounding ends of the first portions in a plan view.

Abstract: A semiconductor device includes, on an n-type semiconductor substrate, a power transistor, an n-type transistor, and a p-type transistor on a laminated semiconductor substrate that laminates an n-type drift layer, a p-type; the power transistor has a trench gate electrode penetrating through the base layer; the p-type transistor is formed in an n-type well region formed in the base layer, and the n-type transistor is formed in a p-type well region further formed in the base layer or n-type well region; and a p-type impurity concentration of the buried channel region of the p-type transistor is equal to a p-type impurity concentration of the base layer.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes preparing a silicon carbide semiconductor substrate of a first conductivity type; forming a first semiconductor layer of a first conductivity type at a surface of the silicon carbide semiconductor substrate, the first semiconductor layer having a first surface and a second surface opposite to each other, the second surface facing the silicon carbide semiconductor substrate; implanting ions of an inert element into a region of a surface layer of the first semiconductor layer, thereby, inducing ion implantation damage to a crystal structure of the region in which a long tail occurs, the surface layer being at the first surface of the first semiconductor layer; and implanting a dopant of a second conductivity type into the surface layer of the first semiconductor layer where the crystal structure is damaged, thereby, forming column regions of the second conductivity type.

Abstract: There is provided a semiconductor equipment including: an element area having an n-type layer, a first p-type layer on the n-type layer, and a second p-type layer on the first p-type layer, the second p-type layer having an acceptor concentration higher than the first p-type layer; and an electric field relaxation region surrounding the element area, in which in the electric field relaxation region, a region containing an impurity element that inactivates a part of acceptors in the first p-type layer and the second p-type layer is provided in the first p-type layer and the second p-type layer.

Abstract: In an active region and an edge termination region, a drift layer is constituted by a same SJ structure with a parallel pn layer. In the edge termination region, a p+-type extension portion between the active region and a JTE structure fixes the JTE structure to the potential of a source electrode. The p+-type extension portion is between and in contact with a p-type base extension portion and the parallel pn layer. The p+-type extension portion is an extension of upper portions of p+-type regions provided in the active region to mitigate electric field near bottoms of gate trenches. Between the p-type base extension portion and the parallel pn layer is free of the lower portions of the p+-type regions. Thus, a length in the depth direction of the p-type column regions of the edge termination region is longer than that of the p-type column regions of the active region.

Abstract: A silicon carbide semiconductor substrate has a silicon carbide semiconductor substrate of a first conductivity type and a first semiconductor layer of the first conductivity type, provided at a front surface of the silicon carbide semiconductor substrate and having a doping concentration lower than that of the silicon carbide semiconductor substrate. A portion of the first semiconductor layer contains a dopant of a second conductivity type. A concentration of the dopant of the second conductivity type in the first semiconductor layer differs in a direction parallel to an orientation flat or in a direction orthogonal to the orientation flat, the orientation flat indicating a crystal axis direction, such that a distribution of a net doping concentration in the first semiconductor layer has a variation equal to or less than a predetermined threshold.

Abstract: One object is to provide a semiconductor device capable of reducing loss during turn-on and degradation of forward voltage. A vertical MOSFET includes a semiconductor substrate 2 of a first conductivity type, a first semiconductor layer 1 of the first conductivity type, a second semiconductor layer 16 of a second conductivity type, first semiconductor regions 17 of the first conductivity type, first trenches 31 and a second trench 32, gate electrodes 20 provided in the first trenches 31 via a gate insulating film 19, and a Schottky electrode 29 provided in the second trench 32. The first trenches 31 are provided in a striped pattern, in a plan view and the second trench 32 surrounds the first trenches 31.

Abstract: A silicon carbide semiconductor device has an n-type silicon carbide semiconductor substrate, an n-type first semiconductor layer, n-type first JFET regions, a p-type second semiconductor layer, n-type first semiconductor regions, and trenches. The first semiconductor layer has an impurity concentration lower than that of the substrate. The first JFET regions are provided in a surface layer of the first semiconductor layer and have an effective donor concentration higher than that of the first semiconductor. The p-type second semiconductor layer is provided at a surface of the first semiconductor layer. The n-type first semiconductor regions are selectively provided in a surface layer of the second semiconductor layer. The trenches penetrate through the first semiconductor regions, the second semiconductor layer, and the first JFET regions. The first JFET regions are doped with an acceptor that is aluminum and a donor that is nitrogen or phosphorus.

Abstract: A control device causes an air conditioning apparatus to execute a temperature adjustment operation of causing a first temperature to approach a first target temperature at a target time point and causing a second temperature to approach a second target temperature at the target time point. The first temperature is a surface temperature of a partition portion including at least one of a floor, a wall, and a ceiling facing a target space. The second temperature is an indoor temperature of the target space.

Abstract: In an active region, a first parallel pn layer in which first first-conductivity-type regions and first second-conductivity-type regions are disposed to repeatedly alternate with one another is provided while in a termination region, a second parallel pn layer in which second first-conductivity-type regions and second second-conductivity-type regions are disposed to repeatedly alternate with one another, a first semiconductor region of the second conductivity type and configuring a voltage withstanding structure, and a second semiconductor region of the second conductivity type are provided. An impurity concentration of each of the plurality of first first-conductivity-type regions and the plurality of second first-conductivity-type regions is reduced in proportion to an impurity concentration of a region directly thereabove. The region directly thereabove is the first semiconductor region or the second semiconductor region.

Abstract: A silicon carbide semiconductor device includes a parallel pn layer that includes a standard portion and first and second portions. The standard portion is located at a center of the parallel pn layer in a depth direction and charge balanced. The first and second portions are respectively located closer to the first and second main surfaces than is the standard portion. In the first portion, an amount of a second-conductivity-type charge is greater than that of the first-conductivity-type regions, and continuously increases with a first gradient in a first direction from the standard portion toward the first main surface. In the second portion, an amount of charge of the first-conductivity-type regions is greater than that of the second-conductivity-type regions, and the amount of charge of the second-conductivity-type regions continuously decreases with a second gradient in a second direction from the standard portion toward the second main surface.

Abstract: A semiconductor device of embodiments includes: a silicon carbide layer having a first face and a second face parallel to a first direction and a second direction perpendicular to the first direction; a first trench, a second trench, and a third trench extending in the first direction; a first region of n-type disposed in the silicon carbide layer; a second region of p-type disposed in the silicon carbide layer, disposed between the first region of n-type and the first face, and disposed between the first trench and the second trench; a sixth region of p-type disposed in the silicon carbide layer and disposed on a bottom surface of the first trench; a seventh region of p-type disposed in the silicon carbide layer and disposed on a bottom surface of the second trench; an eighth region of p-type disposed in the silicon carbide layer and disposed on a bottom surface of the third trench; a ninth region of p-type disposed in the silicon carbide layer and in contact with the sixth region and the second region; and

Abstract: In an active region, a first parallel pn layer is provided in which a plurality of first first-conductivity-type regions and a plurality of first second-conductivity-type regions are disposed so as to repeatedly alternate with one another; in a termination region, a second parallel pn layer is provided in which a plurality of second first-conductivity-type regions and a plurality of second second-conductivity-type regions are disposed so as to repeatedly alternate one another; in the termination region, a first semiconductor region of a second conductivity type, is selectively provided between a first main surface of a semiconductor substrate and the second parallel pn layer, the first semiconductor region configuring a voltage withstanding structure and surrounding a periphery of the active region. An other second-conductivity-type region between the first semiconductor region and the plurality of second second-conductivity-type regions in a thickness direction is provided and has a thickness of 0.