Abstract: A semiconductor device of embodiments includes: a silicon carbide layer having a first face parallel to a first direction and a second direction crossing the first direction and a second face facing the first face; a first trench on a side of the first face extending in the first direction; a second trench extending in the first direction; a third trench extending in the second direction and continuous with the first trench and the second trench; a fourth trench extending in the first direction, disposed between the first trench and the second trench, and spaced from the third trench in the first direction; a gate electrode in the first to fourth trench; a gate insulating layer; a first conductive layer crossing the third trench and connected to the gate electrode; a first electrode disposed on the first face; and a second electrode disposed on the second face.

Abstract: A semiconductor device of embodiments includes: a silicon carbide layer having a first face and a second face; a trench in the silicon carbide layer extending in a first direction; a gate electrode disposed in the trench; a first silicon carbide region of n-type; a second silicon carbide region of p-type between the first silicon carbide region and the first face being shallower than the trench; a third silicon carbide region of n-type disposed between the second silicon carbide region and the first face; a fourth silicon carbide region of n-type disposed between the third silicon carbide region and the first face, a width of the fourth silicon carbide region in a second direction perpendicular to the first direction being smaller than a width of the third silicon carbide region in the second direction; and a first electrode in contact with the fourth silicon carbide region.

Abstract: A semiconductor device including a semiconductor substrate; a first parallel pn layer in which first first-conductivity-type column regions and first second-conductivity-type column regions repeatedly alternate with one another in an active region; a second parallel pn layer in which second first-conductivity-type column regions and second second-conductivity-type column regions repeatedly alternate with one another, in a termination region; a device structure provided between the first main surface of the semiconductor substrate and the first parallel pn layer; a first electrode provided at the first main surface and electrically connected to the device structure; and a second electrode provided at the second main surface of the semiconductor substrate. The plurality of second first-conductivity-type column regions and the plurality of second second-conductivity-type column regions are disposed in concentric shapes surrounding a perimeter of the first parallel pn layer in a plan view.

Abstract: A semiconductor device including a semiconductor substrate, a parallel pn layer and a device structure provided in the semiconductor substrate, first and second electrodes respectively provided at two main surfaces of the semiconductor substrate, the first electrode being electrically connected to the device structure. The parallel pn layer includes first-conductivity-type column regions and second-conductivity-type column regions that are adjacently disposed and repeatedly alternate with one another in a first direction parallel to the first main surface, that each extend in a second direction parallel to the first main surface and orthogonal to the first direction, and that are of a same impurity concentration. A portion of the second-conductivity-type column regions is shorter than the rest thereof. The parallel pn layer has a first portion and a second portion respectively closer to the first and second main surfaces, the first portion being more p-rich, and less n-rich, than the second portion.

Abstract: A silicon carbide semiconductor device, including a semiconductor substrate, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a plurality of trenches, a plurality of gate electrodes respectively provided in the trenches, a first conductive film, a first electrode, a second electrode, a plurality of first high-concentration regions, a plurality of second high-concentration regions, and a second conductive film. The first semiconductor region has a first portion and a plurality of second portions respectively at positions facing the plurality of second high-concentration regions in a depth direction. The second conductive film forms a Schottky contact with the plurality of second portions of the first semiconductor region, such that each junction surface between the second conductive film and the first semiconductor region forms a Schottky barrier of a Schottky barrier diode.

Abstract: A silicon carbide semiconductor device, including a semiconductor substrate having an active region and a termination region that surrounds the active region in a top view, a first parallel pn layer provided in the semiconductor substrate in the active region, a second parallel pn layer provided in the semiconductor substrate in the termination region, a device structure provided in the active region, a first electrode electrically connected to the device structure, a second electrode, a first semiconductor region selectively provided in the termination region, and a second semiconductor region provided between the second parallel pn layer and the first semiconductor region, and in contact with the first semiconductor region. The second parallel pn layer is provided apart from the first semiconductor region, at a position deeper than the first semiconductor region and closer to an end of the semiconductor substrate than an outer end of the first semiconductor region.

Abstract: A semiconductor device has: a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a first semiconductor region of a second conductivity type; a second semiconductor region of the first conductivity type; a trench; a gate insulating film; a gate electrode; a third semiconductor region of the first conductivity type, and a fourth semiconductor region of the second conductivity type. The third semiconductor region is provided between the gate insulating film on a sidewall of the trench and the first semiconductor region. The fourth semiconductor region is provided between the first semiconductor region and the third semiconductor region, and has an impurity concentration higher than that of the first semiconductor region.

Abstract: A superjunction semiconductor device having a termination structure portion surrounding an active region in a plan view. The device includes: a semiconductor substrate; a first semiconductor layer provided on the semiconductor substrate; and a parallel pn structure and a channel stopper provided in the first semiconductor layer. The channel stopper surrounds the parallel pn structure in the plan view, and contacts the parallel pn structure in the termination structure portion. The parallel pn structure includes a plurality of first columns each having a first width and a plurality of second columns each having a second width that repeatedly alternate one another parallel to the main surface. In a region of the parallel pn structure contacting the channel stopper, a product of the second width and an impurity concentration of the second columns is less than a product of the first width and an impurity concentration of the first columns.

Abstract: A silicon carbide semiconductor device, including a semiconductor substrate; a first semiconductor region and a second semiconductor region provided in the semiconductor substrate; a plurality of third semiconductor regions selectively provided in the semiconductor substrate, a plurality of first and second trenches penetrating through the second and third semiconductor regions and reaching the first semiconductor region; a plurality of gate electrodes respectively provided in the first trenches; a plurality of conductive films respectively embedded in the second trenches, junction interfaces between the first semiconductor region and the conductive films forming a plurality of Schottky barriers; a first electrode and a second electrode; and a plurality of Schottky barrier diodes that respectively include the plurality of Schottky barriers.

Abstract: A semiconductor device having a connecting region between an active region and an edge region. The semiconductor device including a semiconductor substrate, a first semiconductor layer provided on the semiconductor substrate, a second semiconductor layer provided on the first semiconductor layer, a plurality of first semiconductor regions selectively provided in the second semiconductor layer, a plurality of first and second trenches penetrating through the first semiconductor regions and the second semiconductor layer, a plurality of gate electrodes provided in the first trenches, via a plurality of gate insulating films, respectively, and a plurality of Schottky electrodes respectively provided in the second trenches. The semiconductor substrate, the first and second semiconductor layers, the first semiconductor regions, the first trenches, the gate electrodes and the gate insulating films are provided in the active region.

Abstract: By a first ion-implantation of a p-type impurity, first and second p+-type regions for mitigating electric field of trench bottoms are formed in surface regions of an n?-type epitaxial layer that constitutes an n?-type drift region. Thereafter, a second ion-implantation of an n-type impurity for reverting a portion of each of the first p+-type regions to the n?-type, and a third ion-implantation of an n-type impurity for an entire surface of the n?-type epitaxial layer, are performed. By the second ion-implantation, first current spreading layer (CSL) portions that constituting n-type current spreading regions are formed facing the first p+-type regions in the depth direction. By the third ion-implantation, the first CSL portions have a predetermined n-type impurity concentration, and second CSL portions constituting the n-type current spreading regions are formed between the first and second p+-type regions and are in contact with the first CSL portions.

Abstract: An n--type drift layer is an n--type epitaxial layer doped with nitrogen as an n-type dopant and is co-doped with aluminum as a p-type dopant, the n--type drift layer containing the nitrogen and aluminum substantially uniformly throughout. An n-type impurity concentration of the n--type drift layer is an impurity concentration determined by subtracting the aluminum concentration from the nitrogen concentration of the n--type drift layer; a predetermined blocking voltage is realized by the impurity concentration. A combined impurity concentration of the nitrogen and aluminum of the n--type drift layer is at least 3×1016/cm3.

Abstract: A semiconductor device of embodiments includes: a silicon carbide layer including a trench, a n-type first SiC region, a p-type second SiC region on the first SiC region, a n-type third SiC region on the second SiC region, a fourth SiC region of p-type between the first trench and the first SiC region, and a fifth SiC region electrically connecting the second SiC region and the fourth SiC region; and a gate electrode in the trench. The first trench has a first region extending in a first direction, a second region continuous with the first region, and a third region continuous with the second region and extending in the first direction. The second width of the second region in the second direction is larger than the first width of the first region in the second direction. The fifth SiC region is disposed in the second direction of the second region.

Abstract: In an entire intermediate region between an active region and an edge termination region, a p+-type region is provided between a p-type base region and a parallel pn layer. The p+-type region is formed concurrently with and in contact with p+-type regions for mitigating electric field near bottoms of gate trenches. The p+-type region has portions that face, respectively, n-type regions and p-type regions of a parallel pn layer in a depth direction Z and at the portions, has protrusions that protrude toward the parallel pn layer. N-type current spreading regions extend in the entire intermediate region from the active region and are between the p+-type region and the parallel pn layer, positioned between protrusions of the p+-type region. The impurity concentration of the n-type current spreading regions in the gate region is higher than that of those in other regions. Thus, avalanche capability may be enhanced.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate has a first main surface, a second main surface, a first impurity region, a second impurity region, and a third impurity region. The first electrode is in contact with each of the second impurity region and the third impurity region on the first main surface. The second electrode is in contact with the first impurity region on the second main surface. The second impurity region includes a first region and a second region disposed between the first region and the second main surface and in contact with the first region. An impurity concentration of the first region is more than or equal to 6×1016 cm?3.

Abstract: A method of manufacturing a superjunction silicon carbide semiconductor device is provided, enabling a reduction of the number of times a combination of epitaxial growth and ion implantation for forming a parallel pn structure is performed. In the method of manufacturing the superjunction silicon carbide semiconductor device, forming an epitaxial layer 2a, 2b of a second conductivity type on a front surface of a silicon carbide semiconductor substrate 1 of a first conductivity type and selectively forming semiconductor regions 4a, 4b of the first conductivity type by implanting nitrogen ions in the epitaxial layer are repeated multiple times, thereby forming the parallel pn structure.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In n?-type drift layer, an n-type region, a lower second p+-type region and a first p+-type region are provided. A part of the lower second p+-type region extends in a direction opposite that of a depth of the trench and is connected to the p-type base layer.

Abstract: A semiconductor device of an embodiment includes a first trench extending in a first direction in a silicon carbide layer; a second trench and a third trench adjacent to each other in the first direction; a first silicon carbide region of n type; a second silicon carbide region of p type on the first silicon carbide region; a third silicon carbide region of n type on the second silicon carbide region; a fourth silicon carbide region of p type between the first silicon carbide region and the second trench; a fifth silicon carbide region of p type between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode, part of which is in the second trench, the first electrode contacting the first silicon carbide region between the fourth silicon carbide region and the fifth silicon carbide region; and a second electrode.

Abstract: A semiconductor device of an embodiment includes: a first trench located in a silicon carbide layer extending in a first direction; a second trench and a third trench adjacent to each other in the first direction; n type first silicon carbide region; p type second silicon carbide region on the first silicon carbide region; n type third silicon carbide region on the second silicon carbide region; p type fourth silicon carbide region between the first silicon carbide region and the second trench; p type fifth silicon carbide region between the first silicon carbide region and the third trench; p type sixth silicon carbide region shallower than the second trench between the second trench and the third trench and having a p type impurity concentration higher than that of the second silicon carbide region; a gate electrode in the first trench; a first electrode, and a second electrode.

Abstract: One object is to provide a semiconductor device capable of reducing loss during turn-on and degradation of forward voltage. A vertical MOSFET includes a semiconductor substrate 2 of a first conductivity type, a first semiconductor layer 1 of the first conductivity type, a second semiconductor layer 16 of a second conductivity type, first semiconductor regions 17 of the first conductivity type, first trenches 31 and a second trench 32, gate electrodes 20 provided in the first trenches 31 via a gate insulating film 19, and a Schottky electrode 29 provided in the second trench 32. The first trenches 31 are provided in a striped pattern, in a plan view and the second trench 32 surrounds the first trenches 31.