Patents by Inventor Shinsuke Harada

Shinsuke Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200291212
    Abstract: An aqueous resin dispersion with which excellent adhesiveness to a polyolefin base material such as a polypropylene base material can be easily obtained, which can be baked at low temperature, and which is for producing an aqueous coating material; and an aqueous coating material and an adhesive which contain the aqueous resin dispersion, are provided. In an aqueous resin dispersion (C) of the present invention, an olefin polymer (A) and a polymer (B) containing a constitutional unit derived from a radically polymerizable monomer (b1) having a reactive functional group are dispersed in an aqueous medium, a median diameter of the aqueous resin dispersion (C) measured by a dynamic light scattering method is 300 nm or less, and a dry product of the aqueous resin dispersion (C) contains 1 mass % or more of an insoluble component (D) that is insoluble in tetrahydrofuran.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Applicant: Mitsubishi Chemical Corporation
    Inventors: Akira HARADA, Shinsuke Haraguchi, Motomi Tanaka, Jun Itou
  • Publication number: 20200283452
    Abstract: The present invention provides compounds represented by formulas (I) to (XVII) or pharmaceutically acceptable salts thereof:
    Type: Application
    Filed: March 3, 2020
    Publication date: September 10, 2020
    Inventors: Yoshiaki Ohashi, Yoshihiko Norimine, Tamaki Hoshikawa, Yu Yoshida, Yoshihisa Kobayashi, Nobuhiro Sato, Koji Hagiwara, Nobuaki Sato, Shinsuke Hirota, Takaaki Harada, Hikaru Yoshimura
  • Patent number: 10770581
    Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 8, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada, Naoki Kumagai
  • Patent number: 10756200
    Abstract: A silicon carbide semiconductor element includes n-type silicon carbide epitaxial layers formed on an n+-type silicon carbide semiconductor substrate, plural p base layers selectively formed in surfaces of the silicon carbide epitaxial layers, a p-type silicon carbide epitaxial layer formed in the silicon carbide epitaxial layer, and a trench penetrating at least the silicon carbide epitaxial layer. The silicon carbide semiconductor element also includes, in a portion of the silicon carbide epitaxial layer, a mesa portion exposing the p base layer. The silicon carbide semiconductor element further includes, between consecutive mesa side faces of the mesa portion, a flat portion substantially parallel to the silicon carbide substrate. The remaining thickness of the exposed p base layer is larger than 0.5 ?m and smaller than 1.0 ?m.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 25, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Yasuhiko Oonishi, Kenji Fukuda, Shinsuke Harada, Masanobu Iwaya
  • Publication number: 20200257870
    Abstract: A symbol reading apparatus for reading a symbol includes a housing having an opening, a transparent window that covers the opening, a light source arranged at a peripheral portion of the inside of the housing and configured to emit light toward the transparent window, a diffusion element arranged between the light source and the transparent window and including a first side and a second side that is opposite to the first side. The first side is closer to the center of the transparent window than the second side but is farther from a surface of the transparent window than the second side along a direction that extends from the light source to the transparent window, and a light receiver by which the light diffused by the diffusion element and reflected by the symbol is received.
    Type: Application
    Filed: December 13, 2019
    Publication date: August 13, 2020
    Inventors: Yoshiya YAMADA, Shinsuke YAJIMA, Shintaro HARADA
  • Patent number: 10727540
    Abstract: According to one embodiment, a secondary battery including a positive electrode, a negative electrode, and an electrolyte is provided. The negative electrode includes titanium-containing oxide and at least one kind of element selected from the group consisting of B, P, Al, La, Zr, Ge, Zn, Sn, Ga, Pb, In, Bi, and Tl. The electrolyte includes lithium ions and a solvent containing water.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: July 28, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Norio Takami, Yasunobu Yamashita, Shinsuke Matsuno, Yasuhiro Harada, Hiroki Inagaki
  • Patent number: 10689741
    Abstract: A method for recycling a Ni-based single crystal superalloy part or unidirectionally solidified superalloy part provided with a thermal barrier coating containing at least a ceramic on a surface of a Ni-based single crystal superalloy substrate or Ni-based unidirectionally solidified superalloy substrate, in which the method including the steps of: melting and desulfurizing a Ni-based single crystal superalloy part or Ni-based unidirectionally solidified superalloy part at a temperature of the melting point or more of the Ni-based single crystal superalloy or Ni-based unidirectionally solidified superalloy and less than the melting point of the ceramic; heating a casting mold for a recycled Ni-based single crystal superalloy part or casting mold for a recycled Ni-based unidirectionally solidified superalloy part to a temperature of the melting point or more of the Ni-based single crystal superalloy or Ni-based unidirectionally solidified superalloy; pouring the desulfurized melted Ni-based single crystal supe
    Type: Grant
    Filed: May 30, 2016
    Date of Patent: June 23, 2020
    Assignee: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Hiroshi Harada, Kyoko Kawagishi, Toshiharu Kobayashi, Tadaharu Yokokawa, Makoto Osawa, Michinari Yuyama, Shinsuke Suzuki, Yuichiro Joh, Satoshi Utada
  • Patent number: 10693002
    Abstract: In an n-type current diffusion region, a first p+-type region underlying a bottom of a trench (gate trench) is provided. In the n-type current diffusion region, a second p+-type region is provided between adjacent trenches, separated from the first p+-type region and in contact with the p-type base region. In the p-type base region, near a side wall of the trench, a third p+-type region is provided a predetermined distance from the side wall of the trench and is separated from the first and the second p+-type regions. The third p+-type region extends in a depth direction, substantially parallel to the side wall of the trench. A drain-side end of the third p+-type region is in contact with the n-type current diffusion region or protrudes a predetermined depth from the interface of the p-type base region and the n-type current diffusion region toward the drain.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: June 23, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Naoyuki Ohse, Shinsuke Harada, Manabu Takei
  • Patent number: 10665668
    Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, an upper second p+-type region, a lower second p+-type region and a first p+-type region are provided. The lower second p+-type region is provided orthogonal to a trench, and a total mathematical area regions that are between the first p+-type region and the p-type base layer and that include the n-type region is at least two times a total mathematical area of regions that are between the first p+-type region and the p-type base layer and that include the upper second p+-type region.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 26, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Naoyuki Ohse, Shinsuke Harada, Takahito Kojima
  • Patent number: 10651270
    Abstract: In a semiconductor device having a first p+-type base region, a second p+-type base region, a high-concentration n-type region selectively formed in an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate; a p-type base layer formed on the n-type silicon carbide epitaxial layer; an n+-type source region and a p++-type contact region selectively formed in a surface layer of the p-type base layer; and a trench formed penetrating the p-type base layer and shallower than the second p+-type base region, in at least a part of the first p+-type base region, a region is shallower than the second p+-type base region as viewed from an element front surface side.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: May 12, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Ohse, Yusuke Kobayashi, Shinsuke Harada, Yasuhiko Oonishi
  • Patent number: 10629725
    Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, first p+-type regions, and a second p+-type region are provided. In a region opposing, in a depth direction, a gate electrode pad connected to a gate electrode, the first p+-type regions are provided with intervals therebetween along a width direction of the trench gate.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: April 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada, Naoyuki Ohse
  • Patent number: 10622446
    Abstract: A semiconductor device includes in an active region in which current flows, an n+-type silicon carbide epitaxial layer of a low concentration and formed on an n+-type silicon carbide substrate; a p-type channel region constituting a channel region; a trench contacting the p-type channel region and having embedded therein an oxide film and a gate electrode; a p+-type base layer arranged beneath the trench; a third n-type CSL layer region contacting the p-type channel region; a second n-type CSL layer region having a maximum impurity concentration higher than that of the third n-type CSL layer region, the maximum impurity concentration being farther on a substrate front side than a top of the p+-type base layer arranged beneath the trench is; and a first n-type CSL layer region contacting the second n-type CSL layer region and having a maximum impurity concentration lower than that of the second n-type CSL layer region.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 14, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Akimasa Kinoshita, Shinsuke Harada
  • Patent number: 10600921
    Abstract: In forming an ohmic electrode on a back surface of an n-type SiC substrate, an n+-type semiconductor region is formed in a surface layer of the back surface of an n-type epitaxial substrate by ion implantation. In this ion implantation, the impurity concentration of the n+-type semiconductor region is a predetermined range and preferably a predetermined value or less, and an n-type impurity is implanted by acceleration energy of a predetermined range such that the n+-type semiconductor region has a predetermined thickness or less. Thereafter, a nickel layer and a titanium layer are sequentially formed on the surface of the n+-type semiconductor region, the nickel layer is heat treated to form a silicide, and the ohmic electrode formed from nickel silicide is formed. In this manner, a back surface electrode that has favorable properties can be formed while peeling of the back surface electrode can be suppressed.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: March 24, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Ohse, Fumikazu Imai, Tsunehiro Nakajima, Kenji Fukuda, Shinsuke Harada, Mitsuo Okamoto
  • Publication number: 20200083368
    Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.
    Type: Application
    Filed: July 22, 2019
    Publication date: March 12, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke KOBAYASHI, Manabu TAKEI, Shinsuke HARADA, Naoki KUMAGAI
  • Patent number: 10546950
    Abstract: At bottom of a gate trench, a conductive layer is provided. A Schottky junction is formed along a side wall of the gate trench by the conductive layer and the n-type current spreading region. The Schottky junction constitutes one unit cell of a trench-type SBD. In the gate trench, a gate electrode is provided on the conductive layer, via an insulating layer. The gate electrode constitutes one unit cell of a trench-gate-type vertical MOSFET. In other words, one unit cell of the trench gate MOSFET and one unit cell of the trench-type SBD are disposed built into a single gate trench and oppose each other in a depth direction.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: January 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Shinsuke Harada
  • Patent number: 10522673
    Abstract: Plural trenches are provided in a semiconductor substrate. First p+-type regions underlie bottoms of the trenches. A MOS gate is embedded in first trenches of the trenches and one unit cell of a trench-gate-type MOSFET is configured. One unit cell of a trench-type SBD is constituted by a Schottky junction formed by an n-type current spreading region and a conductive layer embedded in a second trench of the trenches. Between second trenches in which the trench-type SBD is embedded, at least two of the first trenches in which a MOS gate is embedded are disposed. A sum of widths of all first p+-type regions disposed in a MOS cell region C? that is substantially half of a region between the adjacent second trenches is in a range of about 2 ?m to 8 ?m.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 31, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada
  • Patent number: 10452900
    Abstract: An information processing system includes circuitry that receives position information of first stroke information and second stroke information drawn on a display at different timing, adds additional information indicating a relationship of the received first stroke information and the received second stroke information to the received first stroke information, and generates, based on the position information of the received first stroke information, the position information of the received second stroke information and the added additional information, consecutive data used for displaying (playing) information drawn on the display as the first stroke information and the second stroke information, and a memory that stores the generated consecutive data.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: October 22, 2019
    Assignee: RICOH COMPANY, LTD.
    Inventor: Shinsuke Harada
  • Patent number: 10439060
    Abstract: A semiconductor device includes an n-type silicon carbide epitaxial layer on a front surface of an n+-type silicon carbide substrate. A first p+-type base region is provided in the n-type silicon carbide epitaxial layer and a breakdown voltage structure region is provided in an outer periphery of an active region through which a main current flows. A distance between the first p+-type base region and a front surface of the n+-type silicon carbide substrate is smaller than a distance between the breakdown voltage structure region and the front surface of the n+-type silicon carbide substrate.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: October 8, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Ohse, Shinsuke Harada, Makoto Utsumi, Yasuhiko Oonishi
  • Patent number: 10418477
    Abstract: A silicon carbide semiconductor device, including a silicon carbide substrate, a drift layer provided on a front surface of the silicon carbide substrate, an embedded layer selectively provided in a surface layer of the drift layer, an epitaxial layer provided on the drift layer, a channel layer provided on the epitaxial layer, a source region selectively provided in a surface layer of the channel layer, a trench penetrating the source region and the channel layer and reaching the epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a source electrode in contact with the channel layer and the source region, and a drain electrode provided on a rear surface of the silicon carbide substrate. The embedded layer is arranged underneath the trench in a depth direction. A longitudinal direction of the trench, which is perpendicular to the depth direction, is parallel to the off-direction of the silicon carbide substrate.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: September 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Akimasa Kinoshita, Shinsuke Harada, Yasunori Tanaka
  • Patent number: 10418478
    Abstract: On a surface of an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate, first and second p+-type base regions are formed in the n-type silicon carbide epitaxial layer, an n-type region is formed in the n-type silicon carbide epitaxial layer, a p-type base layer is formed on the n-type region, an n+-type source region and a p++-type contact region are formed in the p-type base layer, and a trench is formed to a position shallower than the second p+-type base region and penetrates the p-type base layer. A first sidewall angle of the trench at a position of the p-type base layer is 80° to 90° with respect to a main surface. A difference of the first sidewall angle and a second sidewall angle of the trench at a position deeper than a boundary of the p-type base layer and the n-type region is 1° to 25°.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: September 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahito Kojima, Shinsuke Harada, Yasuhiko Oonishi