Abstract: Provided is a time-to-digital converter, comprising a phase frequency detector configured to receive a phase-locked loop input clock and a feedback clock, a ring oscillator configured to perform oscillation with multi-phase clocks of a first period, a counter array configured to count the number of oscillations in which the ring oscillator oscillates in a first period by the number of positive integers during the first pulse width, a multiplexer configured to divide the first period into a plurality of zones using edge information of the multi-phase clocks of the ring oscillator, and selects and outputs voltage information of a plurality of neighboring phase clocks included in a first zone from the plurality of zones, an analog-to-digital converter, a calibrator, and a first adder, wherein the calibrator comprises, an offset lookup table generation circuit, a gain-corrected analog-to-digital conversion output generator, and a second adder.

Abstract: Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.

Abstract: A crystal oscillator including a feedback circuit, and a reference clock generating circuit including the crystal oscillator. The crystal oscillator is configured to generate an oscillating signal based on a natural frequency of a crystal. The crystal oscillator may include: a current generating circuit connected to a first node having a first voltage and a second node having a second voltage, and configured to output a first current to the second node; a feedback circuit connected to the generating circuit via the first and second nodes and configured to adjust a level of the second voltage by controlling a level of the first voltage; and a crystal circuit connected to the second node and configured to generate the oscillating signal based on the second voltage.

Abstract: Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.

Abstract: Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.

Abstract: A crystal oscillator including a feedback circuit, and a reference clock generating circuit including the crystal oscillator. The crystal oscillator is configured to generate an oscillating signal based on a natural frequency of a crystal. The crystal oscillator may include: a current generating circuit connected to a first node having a first voltage and a second node having a second voltage, and configured to output a first current to the second node; a feedback circuit connected to the generating circuit via the first and second nodes and configured to adjust a level of the second voltage by controlling a level of the first voltage; and a crystal circuit connected to the second node and configured to generate the oscillating signal based on the second voltage.

Abstract: Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.