Patents by Inventor Shinya Nunoue

Shinya Nunoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190296111
    Abstract: In one embodiment, a semiconductor device is provided with a substrate, a first nitride semiconductor layer above the substrate, a second nitride semiconductor layer which is provided on the first nitride semiconductor layer and is in contact with the first nitride semiconductor layer, a source electrode provided between the substrate and the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a drain electrode provided on the second nitride semiconductor layer and electrically connected to the second nitride semiconductor layer, a gate insulating layer provided at least between the substrate and the first nitride semiconductor layer, a gate electrode between the substrate and the gate insulating layer, and a first insulating layer between the substrate and the gate insulating layer to cover the gate electrode and the source electrode.
    Type: Application
    Filed: August 31, 2018
    Publication date: September 26, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Toshiki Hikosaka, Kenjiro Uesugi, Masahiko Kuraguchi, Shinya Nunoue
  • Patent number: 10395932
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, and first, second, third, fourth, and fifth semiconductor regions. The first electrode includes a first conductive region. The second electrode includes a second conductive region separated. The third electrode includes a third conductive region. The first semiconductor region is separated from the first, second, and third conductive regions. The second semiconductor region is provided between the first conductive and semiconductor regions, between the second conductive and first semiconductor regions, and between the third conductive and first semiconductor regions. The third semiconductor region is provided between the first conductive region and the second semiconductor region. The fourth semiconductor region is provided between the second conductive region and the second semiconductor region.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: August 27, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenjiro Uesugi, Toshiki Hikosaka, Shinya Nunoue
  • Patent number: 10355119
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include forming a trench and exposing a portion of a first film at a bottom portion of the trench by removing a portion of a second film by performing dry etching using a gas including a first element. The second film is provided on the first film. The first film includes Alx1Ga1-x1N (0?x1<1). The second film includes Alx2Ga1-x2N (0<x2<1 and x1<x2). The method can include performing heat treatment while causing the portion being exposed of the first film to contact an atmosphere including NH3, forming an insulating film on the portion of the first film after the heat treatment, and forming an electrode on the insulating film.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: July 16, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenjiro Uesugi, Aya Shindome, Daimotsu Kato, Masahiko Kuraguchi, Shinya Nunoue
  • Publication number: 20190214495
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating layer. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes at least one of Alx1Ga1-x1N (0<x1<1) or p-type Alz1Ga1-z1N (0?z1<1) and has a first surface, a second surface, and a third surface. The second layer includes Alx2Ga1-x2N (0?x2<1 and x2<x1) and includes a first partial region, a second partial region, and a third partial region. The third layer includes Alx3Ga1-x3N (0<x3<1 and x2<x3) and includes a fourth partial region, a fifth partial region, and a sixth partial region.
    Type: Application
    Filed: March 20, 2019
    Publication date: July 11, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jumpei TAJIMA, Toshiki HIKOSAKA, Kenjiro UESUGI, Shigeya KIMURA, Masahiko KURAGUCHI, Shinya NUNOUE
  • Patent number: 10283633
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating layer. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes at least one of Alx1Ga1-x1N (0<x1<1) or p-type Alz1Ga1-z1N (0?z1<1) and has a first surface, a second surface, and a third surface. The second layer includes Alx2Ga1-x2N (0?x2<1 and x2<x1) and includes a first partial region, a second partial region, and a third partial region. The third layer includes Alx3Ga1-x3N (0<x3<1 and x2<x3) and includes a fourth partial region, a fifth partial region, and a sixth partial region.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: May 7, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Toshiki Hikosaka, Kenjiro Uesugi, Shigeya Kimura, Masahiko Kuraguchi, Shinya Nunoue
  • Publication number: 20190088770
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating layer. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes at least one of Alx1Ga1-x1N (0<x1<1) or p-type Alz1Ga1-z1N (0?z1<1) and has a first surface, a second surface, and a third surface. The second layer includes Alx2Ga1-x2N (0?x2<1 and x2<x1) and includes a first partial region, a second partial region, and a third partial region. The third layer includes Alx3Ga1-x3N (0<x3<1 and x2<x3) and includes a fourth partial region, a fifth partial region, and a sixth partial region.
    Type: Application
    Filed: February 20, 2018
    Publication date: March 21, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jumpei TAJIMA, Toshiki HIKOSAKA, Kenjiro UESUGI, Shigeya KIMURA, Masahiko KURAGUCHI, Shinya NUNOUE
  • Patent number: 10186588
    Abstract: According to one embodiment, a semiconductor substrate includes a first semiconductor layer including Alx1Ga1-x1N (0<x1?1) and including carbon and oxygen, and a second semiconductor layer including Alx2Ga1-x2N (0<x2<x1) and including carbon and oxygen. A second ratio of a carbon concentration of the second semiconductor layer to an oxygen concentration of the second semiconductor layer is 730 or more.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: January 22, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daimotsu Kato, Hisashi Yoshida, Jumpei Tajima, Kenjiro Uesugi, Toshiki Hikosaka, Miki Yumoto, Shinya Nunoue, Masahiko Kuraguchi
  • Publication number: 20180374942
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, and first to third semiconductor regions. The third electrode is separated from the second electrode in a first direction. The first semiconductor region includes a first partial region separated from the first electrode, a second partial region separated from the second electrode, and a third partial region separated from the third electrode. The second semiconductor region includes a fourth partial region positioned between the first electrode and the first partial region, a fifth partial region positioned between the second electrode and the second partial region, and a sixth partial region positioned between the third electrode and the third partial region. The third semiconductor region includes a seventh partial region positioned between the second electrode and the fifth partial region and an eighth partial region positioned between the third electrode and the sixth partial region.
    Type: Application
    Filed: February 12, 2018
    Publication date: December 27, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiki HIKOSAKA, Shigeya KIMURA, Shinya NUNOUE, Masahiko KURAGUCHI
  • Publication number: 20180308940
    Abstract: According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain.
    Type: Application
    Filed: May 18, 2018
    Publication date: October 25, 2018
    Applicant: ALPAD CORPORATION
    Inventors: Yoshiyuki Harada, Toshiki Hikosaka, Hisashi Yoshida, Hung Hung, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 10103231
    Abstract: According to one embodiment, a semiconductor device includes a first element portion. The first element portion includes first and second semiconductor layers, first, second and third electrodes, and a first insulating layer. The first semiconductor layer includes Alx1Ga1-x1N (0?x1<1). The first electrode is separated from the first semiconductor layer. The first electrode includes a polycrystal of a nitride of one of Al or B. The second semiconductor layer includes Alx2Ga1-x2N (x1<x2<1). The second semiconductor layer includes first to third regions. The first region is positioned between the second and third regions. The first region is provided between the first semiconductor layer and the first electrode. The first insulating layer is provided between the first region and the first electrode. The second electrode is electrically connected to the second region. The third electrode is electrically connected to the third region.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: October 16, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Koyama, Hisashi Saito, Tatsuo Shimizu, Shinya Nunoue
  • Publication number: 20180219088
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include forming a trench and exposing a portion of a first film at a bottom portion of the trench by removing a portion of a second film by performing dry etching using a gas including a first element. The second film is provided on the first film. The first film includes Alx1Ga1-x1N (0?x1<1). The second film includes Alx2Ga1-x2N (0<x2<1 and x1<x2). The method can include performing heat treatment while causing the portion being exposed of the first film to contact an atmosphere including NH3, forming an insulating film on the portion of the first film after the heat treatment, and forming an electrode on the insulating film.
    Type: Application
    Filed: August 7, 2017
    Publication date: August 2, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenjiro UESUGI, Aya SHINDOME, Daimotsu KATO, Masahiko KURAGUCHI, Shinya NUNOUE
  • Publication number: 20180212046
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and an intermediate region. A position of the first electrode is between a position of the second electrode and a position of the third electrode. The first semiconductor region is separated from the first, second, and third electrodes. The second semiconductor region is provided between the second electrode and the first semiconductor region. The third semiconductor region is provided between the third electrode and the first semiconductor region. The intermediate region includes at least one of a first compound or a second compound. At least a portion of the first electrode is positioned between the second and third semiconductor regions. The intermediate region includes a first partial region, a second partial region, and a third partial region.
    Type: Application
    Filed: August 30, 2017
    Publication date: July 26, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masahiro KOYAMA, Tatsuo Shimizu, Shinya Nunoue
  • Patent number: 10008571
    Abstract: According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: June 26, 2018
    Assignee: ALPAD CORPORATION
    Inventors: Yoshiyuki Harada, Toshiki Hikosaka, Hisashi Yoshida, Hung Hung, Naoharu Sugiyama, Shinya Nunoue
  • Publication number: 20180174849
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, and first, second, third, fourth, and fifth semiconductor regions. The first electrode includes a first conductive region. The second electrode includes a second conductive region separated. The third electrode includes a third conductive region. The first semiconductor region is separated from the first, second, and third conductive regions. The second semiconductor region is provided between the first conductive and semiconductor regions, between the second conductive and first semiconductor regions, and between the third conductive and first semiconductor regions. The third semiconductor region is provided between the first conductive region and the second semiconductor region. The fourth semiconductor region is provided between the second conductive region and the second semiconductor region.
    Type: Application
    Filed: August 7, 2017
    Publication date: June 21, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenjiro UESUGI, Toshiki HIKOSAKA, Shinya NUNOUE
  • Patent number: 9972657
    Abstract: According to one embodiment, a semiconductor light emitting element (110) includes a metal layer (40), a first to a fourth semiconductor layers (10a, 20a, 10b, 20b), a first and a second light emitting layers (30a, 30b), a first to a sixth electrodes (e1-e6), and a first inter-element interconnect section (12). The first semiconductor layer (10a) includes a first to a third regions (r1-r3). The second semiconductor layer (20a) is provided between the first region (r1) and the metal layer (40) and between the second region (r2) and the metal layer (40). The third semiconductor layer (10b) includes a fourth to a sixth regions (r4-r6). The fourth semiconductor layer (20b) is provided between the fourth region (r4) and the metal layer (40) and between the fifth region (r5) and the metal layer (40). The first inter-element interconnect section (12) is provided between the second electrode (e2) and the metal layer (40) and between the sixth electrode (e6) and the metal layer (40).
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: May 15, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Hiroshi Ono, Toshihide Ito, Kenjiro Uesugi, Shinya Nunoue
  • Publication number: 20180101001
    Abstract: A cell selecting apparatus including a light source device for placing a cell sample, the light source device including a plurality of light source elements arranged in a matrix form.
    Type: Application
    Filed: September 8, 2017
    Publication date: April 12, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi HIOKI, Masaki TOHYAMA, Shinya NUNOUE
  • Publication number: 20180076291
    Abstract: According to one embodiment, a semiconductor device includes a first element portion. The first element portion includes first and second semiconductor layers, first, second and third electrodes, and a first insulating layer. The first semiconductor layer includes Alx1Ga1-x1N (0?x1<1). The first electrode is separated from the first semiconductor layer. The first electrode includes a polycrystal of a nitride of one of Al or B. The second semiconductor layer includes Alx2Ga1-x2N (x1<x2<1). The second semiconductor layer includes first to third regions. The first region is positioned between the second and third regions. The first region is provided between the first semiconductor layer and the first electrode. The first insulating layer is provided between the first region and the first electrode. The second electrode is electrically connected to the second region. The third electrode is electrically connected to the third region.
    Type: Application
    Filed: February 22, 2017
    Publication date: March 15, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masahiro KOYAMA, Hisashi Saito, Tatsuo Shimizu, Shinya Nunoue
  • Patent number: 9865770
    Abstract: According to one embodiment, a light emitting element includes n-type and p-type semiconductor layers and a light emitting unit. The light emitting unit is provided between the n-type semiconductor layer and the p-type semiconductor layer, the light emitting unit emits light with a peak wavelength of not less than 530 nm. The light emitting unit includes an n-side barrier layer and a first light emitting layer. The first light emitting layer includes a first barrier layer provided between the n-side barrier layer and the p-type semiconductor layer, a first well layer contacting the n-side barrier layer between the n-side barrier layer and the first barrier layer, a first AlGaN layer provided between the first well layer and the first barrier layer and including Alx1Ga1-x1N (0.15?x1?1), and a first p-side InGaN layer provided between the first AlGaN layer and the first barrier layer and including Inya1Ga1-ya1N (0<ya1?0.1).
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: January 9, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Saito, Rei Hashimoto, Jongil Hwang, Shinya Nunoue
  • Publication number: 20170221962
    Abstract: According to one embodiment, a semiconductor light emitting element (110) includes a metal layer (40), a first to a fourth semiconductor layers (10a, 20a, 10b, 20b), a first and a second light emitting layers (30a, 30b), a first to a sixth electrodes (e1-e6), and a first inter-element interconnect section (12). The first semiconductor layer (10a) includes a first to a third regions (r1-r3). The second semiconductor layer (20a) is provided between the first region (r1) and the metal layer (40) and between the second region (r2) and the metal layer (40). The third semiconductor layer (10b) includes a fourth to a sixth regions (r4-r6). The fourth semiconductor layer (20b) is provided between the fourth region (r4) and the metal layer (40) and between the fifth region (r5) and the metal layer (40). The first inter-element interconnect section (12) is provided between the second electrode (e2) and the metal layer (40) and between the sixth electrode (e6) and the metal layer (40).
    Type: Application
    Filed: July 28, 2015
    Publication date: August 3, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jumpei TAJIMA, Hiroshi ONO, Toshihide ITO, Kenjiro UESUGI, Shinya NUNOUE
  • Patent number: 9679974
    Abstract: According to one embodiment, a nitride semiconductor element includes: a stacked body; and a functional layer. The stacked body includes a first GaN layer, a first layer, and a second GaN layer. The first GaN layer includes a first protrusion. The first layer is provided on the first GaN layer and contains at least one of Si and Mg. The second GaN layer is provided on the first layer and includes a second protrusion. Length of bottom of the second protrusion is shorter than length of bottom of the first protrusion. A functional layer is provided on the stacked body and includes a nitride semiconductor.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: June 13, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Hikosaka, Hisashi Yoshida, Hajime Nago, Naoharu Sugiyama, Shinya Nunoue